LFE3-35EA-8FN672I Lattice, LFE3-35EA-8FN672I Datasheet - Page 119
LFE3-35EA-8FN672I
Manufacturer Part Number
LFE3-35EA-8FN672I
Description
IC FPGA 33.3K LUTS 310I/O FN672
Manufacturer
Lattice
Series
ECP3r
Datasheets
1.LFE3-150EA-7FN672C.pdf
(136 pages)
2.LFE3-35EA-8FN672I.pdf
(4 pages)
3.LFE3-35EA-8FN672I.pdf
(21 pages)
Specifications of LFE3-35EA-8FN672I
Number Of Logic Elements/cells
33000
Number Of Labs/clbs
4125
Total Ram Bits
1358848
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-BBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1163
- LFE3-150EA-7FN672C PDF datasheet
- LFE3-35EA-8FN672I PDF datasheet #2
- LFE3-35EA-8FN672I PDF datasheet #3
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- Download datasheet (3Mb)
Lattice Semiconductor
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
For Left and Right Edges of the Device
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
For Top Edge of the Device
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
Note: “n” is a row PIC number.
PICs Associated with
DQS Strobe
PIO Within PIC
4-4
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
DDR Strobe (DQS) and
LatticeECP3 Family Data Sheet
Data (DQ) Pins
[Edge]DQSn
[Edge]DQSn
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Pinout Information
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