LFE3-35EA-8FN672I Lattice, LFE3-35EA-8FN672I Datasheet - Page 79
LFE3-35EA-8FN672I
Manufacturer Part Number
LFE3-35EA-8FN672I
Description
IC FPGA 33.3K LUTS 310I/O FN672
Manufacturer
Lattice
Series
ECP3r
Datasheets
1.LFE3-150EA-7FN672C.pdf
(136 pages)
2.LFE3-35EA-8FN672I.pdf
(4 pages)
3.LFE3-35EA-8FN672I.pdf
(21 pages)
Specifications of LFE3-35EA-8FN672I
Number Of Logic Elements/cells
33000
Number Of Labs/clbs
4125
Total Ram Bits
1358848
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-BBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1163
- LFE3-150EA-7FN672C PDF datasheet
- LFE3-35EA-8FN672I PDF datasheet #2
- LFE3-35EA-8FN672I PDF datasheet #3
- Current page: 79 of 136
- Download datasheet (3Mb)
Lattice Semiconductor
LatticeECP3 Internal Switching Characteristics
PFU/PFF Logic Mode Timing
t
t
t
t
t
t
t
t
t
PFU Dual Port Memory Mode Timing
t
t
t
t
t
t
t
PIC Timing
PIO Input/Output Buffer Timing
t
t
IOLOGIC Input/Output Timing
t
t
t
t
t
t
t
EBR Timing
t
t
t
t
t
t
t
LUT4_PFU
LUT6_PFU
LSR_PFU
LSRREC_PFU
SUM_PFU
HM_PFU
SUD_PFU
HD_PFU
CK2Q_PFU
CORAM_PFU
SUDATA_PFU
HDATA_PFU
SUADDR_PFU
HADDR_PFU
SUWREN_PFU
HWREN_PFU
IN_PIO
OUT_PIO
SUI_PIO
HI_PIO
COO_PIO
SUCE_PIO
HCE_PIO
SULSR_PIO
HLSR_PIO
CO_EBR
COO_EBR
SUDATA_EBR
HDATA_EBR
SUADDR_EBR
HADDR_EBR
SUWREN_EBR
Parameter
LUT4 delay (A to D inputs to F output)
LUT6 delay (A to D inputs to OFX output)
Set/Reset to output of PFU (Asynchronous)
Asynchronous Set/Reset recovery time for
PFU Logic
Clock to Mux (M0,M1) Input Setup Time
Clock to Mux (M0,M1) Input Hold Time
Clock to D input setup time
Clock to D input hold time
Clock to Q delay, (D-type Register
Configuration)
Clock to Output (F Port)
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Write/Read Enable Setup Time
Write/Read Enable Hold Time
Input Buffer Delay (LVCMOS25)
Output Buffer Delay (LVCMOS25)
Input Register Setup Time (Data Before
Clock)
Input Register Hold Time (Data after Clock)
Output Register Clock to Output Delay
Input Register Clock Enable Setup Time
Input Register Clock Enable Hold Time
Set/Reset Setup Time
Set/Reset Hold Time
Clock (Read) to output from Address or Data
Clock (Write) to output from EBR output Reg-
ister
Setup Data to EBR Memory
Hold Data to EBR Memory
Setup Address to EBR Memory
Hold Address to EBR Memory
Setup Write/Read Enable to EBR Memory
Over Recommended Commercial Operating Conditions
Description
4
3-26
-0.097
-0.137
-0.055
-0.227
-0.085
-0.107
-0.218
-0.071
-0.107
0.134
0.061
0.019
0.188
0.240
0.059
0.956
0.313
0.220
0.117
0.249
0.118
Min.
—
—
—
—
—
—
—
—
—
—
—
-8
0.147
0.273
0.593
0.298
0.243
0.710
0.423
1.115
1.455
Max.
2.78
0.31
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1, 2
DC and Switching Characteristics
LatticeECP3 Family Data Sheet
-0.103
-0.155
-0.257
-0.055
-0.072
-0.094
-0.227
-0.070
-0.106
0.144
0.068
0.013
0.217
0.275
0.059
1.124
0.395
0.185
0.103
0.257
0.098
Min.
—
—
—
—
—
—
—
—
—
—
—
-7
0.163
0.307
0.674
0.345
0.273
0.803
0.466
1.155
1.564
Max.
2.89
0.32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-0.109
-0.174
-0.286
-0.063
-0.058
-0.081
-0.237
-0.068
-0.106
0.153
0.075
0.015
0.246
0.310
0.071
1.293
0.378
0.150
0.088
0.265
0.077
Min.
—
—
—
—
—
—
—
—
—
—
—
-6
0.756
0.391
0.303
0.508
1.196
1.674
0.179
0.342
0.897
Max.
2.99
0.33
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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