LFE3-35EA-8FN672I Lattice, LFE3-35EA-8FN672I Datasheet - Page 87
LFE3-35EA-8FN672I
Manufacturer Part Number
LFE3-35EA-8FN672I
Description
IC FPGA 33.3K LUTS 310I/O FN672
Manufacturer
Lattice
Series
ECP3r
Datasheets
1.LFE3-150EA-7FN672C.pdf
(136 pages)
2.LFE3-35EA-8FN672I.pdf
(4 pages)
3.LFE3-35EA-8FN672I.pdf
(21 pages)
Specifications of LFE3-35EA-8FN672I
Number Of Logic Elements/cells
33000
Number Of Labs/clbs
4125
Total Ram Bits
1358848
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-BBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1163
- LFE3-150EA-7FN672C PDF datasheet
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DC and Switching Characteristics
Lattice Semiconductor
LatticeECP3 Family Data Sheet
1, 2, 3, 4, 5, 6
LatticeECP3 Maximum I/O Buffer Speed (Continued)
Over Recommended Operating Conditions
Buffer
Description
Max.
Units
PCI33
PCI, V
= 3.3V
66
MHz
CCIO
1. These maximum speeds are characterized but not tested on every device.
2. Maximum I/O speed for differential output standards emulated with resistors depends on the layout.
3. LVCMOS timing is measured with the load specified in the Switching Test Conditions table of this document.
4. All speeds are measured at fast slew.
5. Actual system operation may vary depending on user logic implementation.
6. Maximum data rate equals 2 times the clock rate when utilizing DDR.
3-34
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