WG82577LM S LGWR Intel, WG82577LM S LGWR Datasheet - Page 146

• Manufacturer Part Number: WG82577LM S LGWR
• Manufacturer: Intel

Specifications of WG82577LM S LGWR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

10.2.1.2.6
10.2.1.3
10.2.1.3.1
139
Interrupt Acknowledge Auto-Mask - IAM (0x000E0; RW)
Receive Register Descriptions
Receive Control Register - RCTL (0x00100; RW)
31:0
0
1
2
3
4
5
7:6
9:8
11:10
13:12
14
Bit
Bit
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
Type
82577 GbE PHY—Intel
0x0
0b
0b
0b
0b
0b
0b
00b
0b
00b
00b
0b
Reset
Reset
IAM_VALUE. When the CTRL_EXT.IAME bit is set and the
ICR.INT_ASSERTED=1, an ICR read or write has the side effect of writing
the contents of this register to the IMC register.
Reserved. This bit represents a hardware reset of the receive-related
portion of the device in previous controllers, but is no longer applicable.
Only a full device reset CTRL.SWRST is supported. Write as 0b for future
compatibility.
Enable (EN). The receiver is enabled when this bit is 1b. Writing this bit to
0b stops reception after receipt of any in progress packets. All subsequent
packets are then immediately dropped until this bit is set to 1b.
Note that this bit controls only DMA functionality to the host. Packets are
counted by the statistics even when this bit is cleared.
Store bad packets (SBP).
0b = Do not store bad packets.
1b = Store bad packets.
Note that CRC errors before the SFD are ignored. Any packet must have a
valid SFD in order to be recognized by the MAC (even bad packets).
Note: Packet errors are not routed to manageability even if this bit is set.
Unicast promiscuous enable (UPE).
0b = Disabled.
1b = Enabled.
Multicast promiscuous enable (MPE).
0b = Disabled.
1b = Enabled.
Long packet enable (LPE).
0b = Disabled.
1b = Enabled.
Reserved.
Receive Descriptor Minimum Threshold Size (RDMTS). The corresponding
interrupt is set each time the fractional number of free descriptors
becomes equal to RDMTS.
to RDMTS values. See
Descriptor Type (DTYP).
00b = Legacy or extended descriptor type.
01b = Packet split descriptor type.
10b and 11b = Reserved.
Multicast Offset (MO). This determines which bits of the incoming
multicast address are used in looking up the bit vector.
00b = 47:38.
01b = [46:37.
10b = 45:36.
11b = 43:34.
Reserved.
®
5 Series Express Chipset MAC Programming Interface
Section 10.2.1.4.8
Table 85
Description
Description
lists which fractional values correspond
for details regarding RDLEN.