WG82577LM S LGWR Intel, WG82577LM S LGWR Datasheet - Page 30
WG82577LM S LGWR
Manufacturer Part Number
WG82577LM S LGWR
Description
Manufacturer
Intel
Datasheet
1.WG82577LM_S_LGWR.pdf
(195 pages)
Specifications of WG82577LM S LGWR
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5.2
Note:
Table 4.
23
Reset Operation
The reset sources for the 82577 are as follows:
The MAC configures the PHY registers. Other the 82577 registers do not need to be
configured.
The effect of the various reset options on these and other registers is listed in
Table 4
82577 Resets
1. Asserting a 3.3 Vdc power on reset should move the PHY out of power down mode.
2. PHY registers (page 0 in MDIO space and any aliases to page 0) are reset during a PHY soft reset. The rest of
Sources
Internal
POR
PHY Soft
Reset
PCIe Reset
In-Band
Reset
Effects/
• Internal Power On Reset (POR) – The 82577 has an internal mechanism for
• PHY Soft Reset – A PHY reset caused by writing to bit 15 in MDIO register 0.
• PCIe Reset - After asserting a PCIe reset, the 82577 stops the PCIe interface and
• In-Band Reset - An in-band message causing complete reset of the 82577 except
the 82577’s MDIO space is not reset.
1
sensing the power pins. Until power is up and stable, the 82577 generates an
internal active low reset. This reset acts as a master reset for the 82577. While the
internal reset is 0b, all registers in the 82577 are reset to their default values.
Strapping values are latched after Internal POR is de-asserted.
Setting the bit resets the PHY, but does not reset non-PHY parts. Soft reset is used
mainly to program the PHY to a different work point without affecting functionality
of the rest of the device. Once the PHY completes its internal reset, a reset
complete indication is sent to the MAC over the interconnect. The MAC then
configures the PHY.
if in the middle of transmitting a packet it will be dropped. De-asserting PCIe reset
resets the internal FIFO unless wake-up is activated and causes a switch from
SMBus to PCIe.
the wake up filters content.
2
lists the impact of each the 82577 reset.
PCIe
Interface
Non-PHY
Registers
and State
PHY
Registers
and State
Reset
Complete
Indication
Strapping
Options
Fuse
Registers
82577 GbE PHY—Initialization
Move Out
of Power
Down
Mode
Wake Up
Register
Table
4.
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