WG82577LM S LGWR Intel, WG82577LM S LGWR Datasheet - Page 16

• Manufacturer Part Number: WG82577LM S LGWR
• Manufacturer: Intel

Specifications of WG82577LM S LGWR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2.5
Figure 2.
9
Intel® 5 Series Express Chipset/82577 – SMBus/PCIe
Interconnects
The 82577 can be connected to any x1 PCIe port in Intel
The PCIe port that connects to the 82577 is selected by PCHSTRP9, bits [11:8] in the
SPI Flash descriptor region. For more information on this setting, please refer to the
Intel
Express Chipset-to-82577 PCIe port connection in the reference schematic must match
the previously mentioned Intel
another port can result in unexpected system behavior.
The SMBus/PCIe interface can be configured in as shown
Intel® 5 Series Express Chipset/82577 Interconnects
Notes:
1. Any free PCIe ports (ports 1-8) can be used to connect to the 82577 PCIe Interface.
2. Any CLKOUT_PCIE[7:0] and PCIECLKRQ[7:0] can be used to connect to PE_CLK for the 82577. Also,
3. PETp/n, PERp/n, PE_CLKp/n should be routed as differential pair as per the PCIe specification.
4. If connecting to PCIECLKRQ[1:2]#, the CLK_REQ_N pull-up resistor should be connected to +V3.3S. Refer to
the CLK_REQ_N guidance section in the Intel
PCIECLKRQ[7:0] can be connected to CLK_REQ_N for the 82577. Stuff empty resistor pad with respective
resistor in the 82577.
®
5 Series Express Chipset External Datasheet Specification. The Intel
Intel® 5 Series
LAN_PHY_PWR_CTRL/
GPIO12
CLKOUT_PCIE[7:0]P
CLKOUT_PCIE[7:0]N
PCIECLKRQ[7:0]#
SML0DATA
PERp[8:1]
PERn[8:1]
SML0CLK
PETp[8:1]
PETn[8:1]
®
2.2k
5%
5 Series Express Chipset SPI strap setting. Choosing
+V3.3A
100nF
100nF
®
2.2k
5%
5 Series Family PDG for more details.
SMBus
0 ohm
10k
+V3.3A
PCIe
EMPTY
10k
+V3.3M_LAN
4
100nF
100nF
10k
®
PERp
PERn
PETp
PETn
CLK_REQ_N
LAN_DISABLE_N
PE_CLKP
PE_CLKN
SMBDATA
Figure
SMBCLK
5 Series Express Chipset.
82577 GbE PHY—Interconnects
2.
Intel® PHY
®
5 Series