WG82577LM S LGWR Intel, WG82577LM S LGWR Datasheet - Page 63
WG82577LM S LGWR
Manufacturer Part Number
WG82577LM S LGWR
Description
Manufacturer
Intel
Datasheet
1.WG82577LM_S_LGWR.pdf
(195 pages)
Specifications of WG82577LM S LGWR
Lead Free Status / Rohs Status
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Programmer’s Visible State—82577 GbE PHY
Table 19.
Note:
Table 20.
1000BASE-T Control PHY Register - Address 9
Logically, bits 12:8 can be regarded as an extension of the Technology Ability field in
register 4.
1000BASE-T Status Register - Address 10
15:13
12
11
10
9
8
7:0
15
14
13
12
11
Bits
Bits
Master/Slave
Configuration
Fault
Master/Slave
Configuration
Resolution
Local Receiver
Status
Remote
Receiver Status
Link Partner
1000BASE-T
Full-Duplex
Capability
Test Mode
Master/Slave
Manual
Configuration
Enable
Master/Slave
Configuration
Value
Port Type
Advertise
1000BASE-T Full-
Duplex Capability
Advertise
1000BASE-T
Half-Duplex
Capability
Reserved
Field
Field
RO,LH,
SC
RO
RO
RO
RO
Type
R/W
R/W
R/W
R/W
R/W
R/W
RO
Type
0b
0b
0b
0b
0b
Default
000b
0b
0b
X
X
X
0x00
Default
Once set, this bit remains set until cleared by the
following actions:
1b = Master/slave configuration fault detected.
0b = No master/slave configuration fault detected.
This bit is not valid when bit 15 is set.
1b = Local PHY resolved to master.
0b = Local PHY resolved to slave.
1b = Local receiver is correct.
0b = Local receiver is incorrect.
1b = Remote receiver is correct.
0b = Remote receiver is incorrect.
1b = Link partner 1000BASE-T full-duplex capable.
0b = Link partner not 1000BASE-T full-duplex capable.
Note: Logically, bits 11:10 might be regarded as an
extension of the Technology Ability field in register 5.
• Read of register 10 via the management interface.
• Reset.
• Auto-negotiation completed.
• Auto-negotiation enabled.
000b = Normal mode.
001b = Test Mode 1 - Transmit waveform test.
010b = Test Mode 2 - Master transmit jitter test.
011b = Test Mode 3 - Slave transmit jitter test.
100b = Test Mode 4 - Transmit distortion test.
101b, 110b, 111b = Reserved.
1b = Enables master/slave configuration.
0b = Automatic master/slave configuration.
Setting this bit has no effect unless address 9, bit
12 is set.
1b = Configures PHY as a master.
0b = Configures PHY as a salve.
1b = Multi-port device (prefer master).
0b = Single port device (prefer slave).
1b = Advertises 1000BASE-T full-duplex capability.
0b = Advertises no 1000BASE-T full-duplex
capability.
1b = Advertises 1000BASE-T half-duplex capability.
0b = Advertises no 1000BASE-T half-duplex
capability.
Set these bits to 0x00.
Description
Description
56
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