TE28F800B3TA110 Intel, TE28F800B3TA110 Datasheet - Page 31

• Manufacturer Part Number: TE28F800B3TA110
• Manufacturer: Intel

Specifications of TE28F800B3TA110

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 110ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

5.2
Datasheet
DQ
DQ
Symbol
A
Table 8. B3 Flash memory Device Signal Descriptions (Sheet 1 of 2)
V
WE#
WP#
OE#
0
8
CE#
RP#
V
0
–A
–DQ
CCQ
–DQ
CC
21
15
7
Signal Descriptions
Table 8, “B3 Flash memory Device Signal Descriptions” on page
Output
Output
Power
Input/
Input/
Type
Input
Input
Input
Input
Input
Input
Input
ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or
erase cycle.
28F008B3: A[0-19], 28F016B3: A[0-20],
28F800B3: A[0-18], 28F160B3: A[0-19],
28F320B3: A[0-20], 28F640B3: A[0-21]
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a
Program command. Inputs commands to the Command User Interface when CE# and WE# are
active. Data is internally latched. Outputs array, identifier and Status Register data. The data pins
float to tristate when the chip is de-selected or the outputs are disabled.
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a
Program command. Data is internally latched. Outputs array and identifier data. The data pins
float to tristate when the chip is de-selected. Not included on x8 products.
CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers.
CE# is active low. CE# high de-selects the memory device and reduces power consumption to
standby levels.
OUTPUT ENABLE: Enables the device’s outputs through the data buffers during a Read
operation. OE# is active low.
WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active
low. Addresses and data are latched on the rising edge of the second WE# pulse.
RESET/DEEP POWER-DOWN: Uses two voltage levels (V
down mode.
When RP# is at logic low, the device is in reset/deep power-down mode , which drives the
outputs to High-Z, resets the Write State Machine, and minimizes current levels (I
When RP# is at logic high, the device is in standard operation . When RP# transitions from
logic-low to logic-high, the device defaults to the read array mode.
WRITE PROTECT: Provides a method for locking and unlocking the two lockable parameter
blocks.
When WP# is at logic low, the lockable blocks are locked , preventing Program and Erase
operations to those blocks. If a Program or Erase operation is attempted on a locked block, SR.1
and either SR.4 [program] or SR.5 [erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked and can be programmed or
erased.
See
OUTPUT V
If the V
power operation (see
This input can be tied directly to V
DEVICE Power Supply: 2.7 V to 3.6 V
Section 12.0, “Block Locking” on page 60
CC
is regulated to 2.7 V to 2.85 V, V
CC
: Enables all outputs to be driven to 1.8 V to 2.5 V while the V
Section 7.2, “DC Voltage Characteristics” on page 37
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
CC
(2.7 V to 3.6 V).
Description
CCQ
for details on write protection.
can be driven at 1.65 V to 2.5 V to achieve lowest
IL
, V
31describes the active signals.
IH
) to control reset/deep power-
CC
) .
is at 2.7 V to 3.3 V.
CCD
).
31