MT48LC8M16A2P-6A Micron Technology Inc, MT48LC8M16A2P-6A Datasheet - Page 37
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MT48LC8M16A2P-6A
Manufacturer Part Number
MT48LC8M16A2P-6A
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC8M16A2P-6A.pdf
(74 pages)
Specifications of MT48LC8M16A2P-6A
Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
5.4ns
Maximum Clock Rate
167MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
165mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC8M16A2P-6A
Manufacturer:
MT
Quantity:
162
Part Number:
MT48LC8M16A2P-6A
Manufacturer:
MICRON/美光
Quantity:
20 000
Part Number:
MT48LC8M16A2P-6A AIT:L
Manufacturer:
MICRON/美光
Quantity:
20 000
Company:
Part Number:
MT48LC8M16A2P-6A IT:L
Manufacturer:
MICRON
Quantity:
250
Company:
Part Number:
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Manufacturer:
MICRON
Quantity:
7 660
Part Number:
MT48LC8M16A2P-6A:L
Manufacturer:
MICRON/美光
Quantity:
20 000
Part Number:
MT48LC8M16A2P-6AG
Manufacturer:
MICRON/美光
Quantity:
20 000
Company:
Part Number:
MT48LC8M16A2P-6AIT
Manufacturer:
NXP
Quantity:
23 000
Part Number:
MT48LC8M16A2P-6AIT:L
Manufacturer:
MICRON/美光
Quantity:
20 000
Figure 27:
Clock Suspend
Figure 28:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
Power-Down
Clock Suspend During WRITE Burst
COMMAND
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered low. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figure 28 and Figure 29 on page 38.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
INTERNAL
CLK
CKE
COMMAND
ADDRESS
All banks idle
Enter power-down mode
CLOCK
CKE
CLK
D
IN
t CKS
NOP
T0
NOP
BANK,
WRITE
COL n
T1
D
Input buffers gated off
n
IN
37
TRANSITIONING DATA
T2
(
(
(
)
(
)
)
(
)
)
(
(
(
(
)
(
)
)
)
)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Exit power-down mode
T3
NOP
n + 1
T4
D
IN
> t CKS
128Mb: x4, x8, x16 SDRAM
DON’T CARE
NOP
T5
n + 2
NOP
D
IN
©1999 Micron Technology, Inc. All rights reserved.
DON’T CARE
ACTIVE
Operations
t RCD
t RAS
t RC