MT48LC8M16A2P-6A Micron Technology Inc, MT48LC8M16A2P-6A Datasheet - Page 40
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MT48LC8M16A2P-6A
Manufacturer Part Number
MT48LC8M16A2P-6A
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC8M16A2P-6A.pdf
(74 pages)
Specifications of MT48LC8M16A2P-6A
Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
5.4ns
Maximum Clock Rate
167MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
165mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC8M16A2P-6A
Manufacturer:
MT
Quantity:
162
Part Number:
MT48LC8M16A2P-6A
Manufacturer:
MICRON/美光
Quantity:
20 000
Part Number:
MT48LC8M16A2P-6A AIT:L
Manufacturer:
MICRON/美光
Quantity:
20 000
Company:
Part Number:
MT48LC8M16A2P-6A IT:L
Manufacturer:
MICRON
Quantity:
250
Company:
Part Number:
MT48LC8M16A2P-6A:L
Manufacturer:
MICRON
Quantity:
7 660
Part Number:
MT48LC8M16A2P-6A:L
Manufacturer:
MICRON/美光
Quantity:
20 000
Part Number:
MT48LC8M16A2P-6AG
Manufacturer:
MICRON/美光
Quantity:
20 000
Company:
Part Number:
MT48LC8M16A2P-6AIT
Manufacturer:
NXP
Quantity:
23 000
Part Number:
MT48LC8M16A2P-6AIT:L
Manufacturer:
MICRON/美光
Quantity:
20 000
Figure 32:
Figure 33:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
Internal
States
Internal
States
WRITE With Auto Precharge Interrupted by a READ
WRITE With Auto Precharge Interrupted by a WRITE
Notes:
Notes:
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
CLK
CLK
DQ
DQ
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
1. DQM is LOW.
1. DQM is LOW.
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
m (Figure 33).
Page Active
Page Active
T0
T0
NOP
NOP
t
WR is met, where
WRITE - AP
WRITE - AP
BANK n,
BANK n,
Page Active
Page Active
BANK n
BANK n
COL a
COL a
T1
D
T1
D
a
a
IN
IN
WRITE with Burst of 4
WRITE with Burst of 4
a + 1
a + 1
T2
T2
D
D
NOP
NOP
IN
IN
t
WR begins when the WRITE to bank m is registered. The last
40
BANK m,
READ - AP
T3
COL d
T3
a + 2
BANK m
D
NOP
IN
Interrupt Burst, Write-Back
t
READ with Burst of 4
WR - BANK n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK m,
WRITE - AP
TRANSITIONING DATA
TRANSITIONING DATA
COL d
BANK m
T4
CL = 3 (BANK m)
T4
D
NOP
d
Interrupt Burst, Write-Back Precharge
t
IN
WR - BANK n
WRITE with Burst of 4
T5
T5
d + 1
NOP
NOP
D
IN
Precharge
t
128Mb: x4, x8, x16 SDRAM
RP - BANK n
T6
T6
D
NOP
d + 2
NOP
D
OUT
t
d
RP - BANK n
IN
©1999 Micron Technology, Inc. All rights reserved.
DON’T CARE
DON’T CARE
T7
T7
d + 3
D
d + 1
NOP
NOP
D
t
t
OUT
RP - BANK m
WR - BANK m
IN
Write-Bac k
Operations