MT29F4G08ABBDAH4:D Micron Technology Inc, MT29F4G08ABBDAH4:D Datasheet - Page 22
MT29F4G08ABBDAH4:D
Manufacturer Part Number
MT29F4G08ABBDAH4:D
Description
MICMT29F4G08ABBDAH4:D 4G SLC NAND FLASH
Manufacturer
Micron Technology Inc
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Asynchronous Addresses
Figure 14: Asynchronous Address Latch Cycle
PDF: 09005aef83b25735
m60a_4gb_nand.pdf – Rev. J 9/11 EN
WE#
ALE
I/Ox
CLE
CE#
An asynchronous address is written from I/O[7:0] to the address register on the rising
edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH.
Bits that are not part of the address space must be LOW (see Device and Array Organiza-
tion). The number of cycles required for each command varies. Refer to the command
descriptions to determine addressing requirements.
Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
addresses are accepted by die (LUNs) even when they are busy; for example, like ad-
dress cycles that follow the READ STATUS ENHANCED (78h) command.
t CS
t CLS
t WP
t ALS
t DS
add 1
Col
t WC
t DH
t ALH
t WH
add 2
Col
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
22
Asynchronous Interface Bus Operation
add 1
Row
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Row
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