MT29F4G08ABBDAH4:D Micron Technology Inc, MT29F4G08ABBDAH4:D Datasheet - Page 23
MT29F4G08ABBDAH4:D
Manufacturer Part Number
MT29F4G08ABBDAH4:D
Description
MICMT29F4G08ABBDAH4:D 4G SLC NAND FLASH
Manufacturer
Micron Technology Inc
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Asynchronous Data Input
Figure 15: Asynchronous Data Input Cycles
PDF: 09005aef83b25735
m60a_4gb_nand.pdf – Rev. J 9/11 EN
WE#
I/Ox
CE#
ALE
CLE
Data is written from I/O[7:0] to the cache register of the selected die (LUN) on the rising
edge of WE# when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH.
Data input is ignored by die (LUNs) that are not selected or are busy (RDY = 0). Data is
written to the data register on the rising edge of WE# when CE#, CLE, and ALE are LOW,
and the device is not busy.
Data is input on I/O[7:0] on x8 devices and on I/O[15:0] on x16 devices.
t
ALS
t
WP
t
DS
D
IN
t
WC
M
t
DH
t
WH
t
WP
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
t
D
DS
IN
23
M+1
t
DH
Asynchronous Interface Bus Operation
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
WP
t
DS
D
IN
N
t
t
t
CLH
DH
CH
© 2009 Micron Technology, Inc. All rights reserved.
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