H5TQ2G63BFR-H9C HYNIX SEMICONDUCTOR, H5TQ2G63BFR-H9C Datasheet - Page 23

• Manufacturer Part Number: H5TQ2G63BFR-H9C
• Description: 58T1898
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H5TQ2G63BFR-H9C

• Memory Type: SDRAM
• Memory Configuration: 128M X 16
• Access Time: 13.5ns
• Interface Type: CMOS
• Memory Case Style: FBGA
• No. Of Pins: 96
• Operating Temperature Range: 0°C To +85°C
• Memory Size: 2 Gbit
• Rohs Compliant: Yes

Rev. 0.5 / Aug. 2010
1.10.2 MPR Functional Description
• One bit wide logical interface via all DQ pins during READ operation.
• Register Read on x16:
• Addressing during for Multi Purpose Register reads for all MPR agents:
• Regular interface functionality during register reads:
• DQL[7:1] and DQU[7:1] either drive the same information as DQ[0], or they drive 0b.
• BA[2:0]: don’t care
• A[1:0]: A[1:0] must be equal to ‘00’b.Data read burst order in nibble is fixed.
• A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7],* For Burst Chop 4
• A[9:3]: don’t care
• A10/AP: don’t care
• A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0.
• A11,A13,...(if available): don’t care
• Support two Burst Ordering which are switched with A2 and A[1:0]=00b.
• Support of read burst chop (MRS and on-the-fly via A12/BC)
• All other address bits (remaining column address bits including A10, all bank address bits) will be
• Regular read latencies and AC timings apply.
• DLL must be locked prior to MPR Reads.
cases, the burst order is switched on nibble base A[2]=0b, Burst order: 0,1,2,3* A[2]=1b, Burst order:
4,5,6,7*
ignored by the DDR3 SDRAM.
Note: * Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the
selected MPR agent.
H5TQ2G63BFR
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