ST52T440F3M6 STMicroelectronics, ST52T440F3M6 Datasheet - Page 34

• Manufacturer Part Number: ST52T440F3M6
• Description: MCU 8-Bit ST52 CISC 8KB EPROM 5V 20-Pin SO
• Manufacturer: STMicroelectronics

Specifications of ST52T440F3M6

• Package: 20SO
• Family Name: ST52
• Maximum Speed: 20 MHz
• Ram Size: 256 Byte
• Program Memory Size: 8 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 13
• On-chip Adc: 6-chx12-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 1

ST52T400/T440/E440/T441
The locations 0, 1 and 2 contain the jump instruc-
tion to the first code line. This instruction is auto-
matically inserted by the Assembler tool. The
operations that can be performed on EPROM dur-
ing the Programming Phase are: Stand By, Mem-
ory Writing, Reading and Verify/Margin Mode,
Memory Lock, IDCode Writing and Verify.
The operations above are managed by using the
4-bit EPROM Control Register. The reading phase
is executed with V
Margin Mode phase needs V
Blank Check must be a reading operation with
V
Table 3.1 illustrates the EPROM Control Register
codes used to select the operation. Programming
of the EPROM Control Register is described
below.
3.1 EPROM Programming Phase Procedure
Programming mode is selected by applying
12V 5% voltage or 5V 5% voltage to the V
and setting the RESET pin =Vss
If the V
performed.
RST_ADD (PB0), INC_ADD (PB1), RST_CONF
(PB2), INC_CONF (PB3) and PHASE (PB7) are
Figure 3.2 EPROM Programming Timing
34/94
PP
= 5V 5%.
PP
RST_CONF
INC_CONF
RST_ADD
INC_ADD
voltage is 5V 5% only reading may be
PHASE
PA(0:7)
PP
= 5V 5%, while the verify/
MEMORY UNLOCK
PP
= 12V 5%. The
100nS
DATA
DATA
OUT
PP
LOCATION ADDRESS =1
pin
MEMORY WRITING
the control signals applied during Programming
Mode.
The signals RST_ADD, RST_CONF and PHASE
are active on level, the others are active on rising
edge.
The signals RST_ADD and PHASE are active low,
signal on RST_CONF is active high.
Data in/out digital signals are transferred through
the pins of Port A.
The memory may be locked by means of the
Memory Lock Status flag, that is used to enable
EPROM operations.
If Memory Lock Status flag is 1 all EPROM opera-
tions are enabled, otherwise, it is only possible to
read (and verify) the OTP code and the Memory
Lock Status flag.
Only If EPROM is not locked by means of Lock
Cell (see paragraph EPROM Locking), may
EPROM operations be enabled, changing the
Memory Lock Status flag from 0 to 1.
The signal RST_ADD (PB0) resets the memory
address register and the Memory Lock Status flag.
Therefore, when the RST_ADD becomes high,
the memory must be unlocked in order to read or
write.
The signal RST_CONF (PB2) resets the EPROM,
DATA
DATA
IN
10 S
DATA
OUT
MEMORY VERIFY
MARGIN MODE
DATA
DATA
OUT