ST52T440F3M6 STMicroelectronics, ST52T440F3M6 Datasheet - Page 38

• Manufacturer Part Number: ST52T440F3M6
• Description: MCU 8-Bit ST52 CISC 8KB EPROM 5V 20-Pin SO
• Manufacturer: STMicroelectronics

Specifications of ST52T440F3M6

• Package: 20SO
• Family Name: ST52
• Maximum Speed: 20 MHz
• Ram Size: 256 Byte
• Program Memory Size: 8 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 13
• On-chip Adc: 6-chx12-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 1

ST52T400/T440/E440/T441
4.2 Global Interrupt Request Enabling
When an Interrupt occurs, it generates a Global
Interrupt Pending (GIP), which can be masked by
software. After a GIP, a Global Interrupt Request
(GIR) will be generated and an Interrupt Service
Routine associated to the interrupt with higher pri-
ority will start. In order to avoid possible conflicts
between interrupt masking set in the main pro-
gram, or inside macros, the GIP is masked
through the User Global Interrupt Mask or the
Macro Global Interrupt Mask (see Figure 4.3).
UEGI/UDGI instruction switches the User Global
Interrupt Mask on/off, enabling/disabling the GIR
for the main program.
MEGI/MDGI instructions switches the Macro Glo-
bal Interrupt Mask on/off in order to ensure that
the macro will not be broken.
4.3 Interrupt Sources
ST52x400/440/441 manages interrupt signals
generated by the internal peripherals (PWM/
TIMER, TRIAC Driver and Analog Comparator) or
deriving from the External Interrupt on pin PA7.
The External Interrupt can be programmed to be
active on the rising or falling edge of INT/PA7 sig-
nal by setting the PEXTINT bit of the Configura-
tion Register to 0.
WARNING: Changing the interrupt priority an
interrupt request is generated.
Each peripheral can be programmed in order to
generate the associated interrupt; further details
are described in the related chapter.Configuration
Register 0 is also used to enable/disable the
Brown-Out (see the related chapter).
4.4 Interrupt Maskability
The interrupts can be masked by configuring the
Configuration Register 0 by means of an LDCR or
an LDCE instruction. The interrupt is enabled
when the bit associated to the mask interrupt is
“1". Viceversa, when the bit is ”0", the interrupt is
masked and is kept pending.
For example:
LDRC 10,6
Register 10)
LDCR 0,10
stored in RAM Register 10)
the result is REG_CONF0=00000110, enabling
the interrupts coming from the Analog Comparator
(INT_AC) and from the PWM/TIMER (INT_PWM/
TIMER).
38/94
(sets REG_CONF0 with the value
(loads the constant 6 in the RAM
Table 4.1 Configuration Register 0
Reset Configuration ‘00000000’
(*) Not Used in ST52x400 devices
Bit
0
1
2
3
4
5
6
7
MSKAC(*)
MSKTRR
MSKTRP
PEXTINT
MSKTRF
MSKTM
MSKBR
Description
MSKE
Name
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
External Interrupt
External Interrupt
Interrupt Masked
Interrupt active
on Falling Edge
on Rising Edge
Interrupt active
Edge Interrupt
Edge Interrupt
Edge Interrupt
Edge Interrupt
TRIAC Falling
TRIAC Falling
TRIAC Rising
TRIAC Rising
TRIAC Pulse
PWM/TIMER
PWM/TIMER
TRIAC Pulse
Description
Interrupt Not
Interrupt Not
Not Masked
Comparator
Comparator
Not Masked
Not Masked
Not Masked
Brown-Out
Brown-Out
Disabled
Interrupt
Interrupt
Interrupt
External
External
Enabled
Masked
Masked
Masked
Masked
Masked
Masked
Analog
Analog