ST52T440F3M6 STMicroelectronics, ST52T440F3M6 Datasheet - Page 68

• Manufacturer Part Number: ST52T440F3M6
• Description: MCU 8-Bit ST52 CISC 8KB EPROM 5V 20-Pin SO
• Manufacturer: STMicroelectronics

Specifications of ST52T440F3M6

• Package: 20SO
• Family Name: ST52
• Maximum Speed: 20 MHz
• Ram Size: 256 Byte
• Program Memory Size: 8 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 13
• On-chip Adc: 6-chx12-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 1

ST52T400/T440/E440/T441
2) The firing pulse is reset to “0" after the time Tp
fixed by program.
3) On the falling edge of MAIN2 the firing pulse is
set to “1"
4) The firing pulse is reset to “0" after the time Tp
fixed by program.
It is possible to generate a programmable Inter-
rupt in the following ways:
1) No Interrupt;
2) Interrupt on the rising edge of the signal Tb
(INT_R)
3) Interrupt on the falling edge of the signal Tb
(INT_F)
4) Interrupt on both edges of the signal Tb.
5) Interrupt on each Triac pulse (INT_P)
If pulse width or TRIAC_COUNT are set to zero,
no pulse on TROUT pin is generated and INT_P
interrupt does not occur.
The Interrupt sources described above are always
active;
REG_CONF0(5:3) bits, INTSL (see Table 4.1).
10.4 Phase Angle Partialization Working Mode
In this mode Triac is controlled each semi-period
of the mains voltage. The power transferred to the
load is proportional to the CURRENT FLOW
ANGLE . This kind of Triac control is suitable to
drive the Triac with inductive load (i.e. universal or
monophase motors). Figure 10.8 illustrates the
relation between the Phase Angle
rent Flow Angle
The peripheral allows to control the Phase Angle
or equivalently time T1 (see Figure 10.9). It is pos-
sible to change Time T1 setting the contents of the
TRIAC_COUNT register (Output Register 9). T1 is
proportional
TRIAC_COUNT register.
Different circuits for the zero crossing detection
may be used, but MAIN1 signal rising edge must
always be synchronized with the mains voltage
zero crossing and MAIN2 signal falling edge must
be synchronized with the following mains voltage
zero crossing.
By using the external circuit illustrated in Figure
10.10, only one synchronization signal from the
mains may be used, MAIN1. In this case,
REG_CONF10(6) must be set to “1”, MAIN2 sig-
nal coincides internally with MAIN1 and MAIN2 pin
is left free for other functions. If main voltage fre-
quency is equal to 50 Hz, then Tr is equal to 20 ms
68/94
of MAIN1.
they
to
can
the
be
value
masked
loaded
and the Cur-
through
in
the
(Figure 10.9) and T1 is:
being T
caler value (Configuration Registers 8 and 9).
NOTE: The user must verify that time T1 is not
larger than a fixed time Tmax (8ms at 50 Hz) in
order to avoid the firing of the Triac in the second
half period of the mains voltage and to choose a
suitable Prescaler value to avoid the shifting of the
pulse sequence in the following semi-period.
In order to avoid problems for the Triac firing when
the load is inductive 8 different pulses are gener-
ated by the peripheral (Figure 10.10). Their width,
equal the semiperiod Ti/2, is programmable by
using registers REG_CONF19 (UTPMSB) and
REG_CONF20 (UTPLSB) and is provided by the
formula:
NOTE: the choice of UTP value must be done by
the user paying attention to the fact that the dura-
tion of the 8 pulses train must be such that added
to T1, it does not fall into the second half period of
the mains voltage. In fact by using a clock master
equal to 20 MHz and the full 16 bit value by
ConfReg19 and 20, the pulse width would be in
the range [0.2, 3.28] ms.
The duty cycle of Ti pulse is always 50%. The
choice of the pulse width must be done according
to TRIAC device specifics and must be set from
the beginning of the program. To change width
during program execution it is necessary to
RESET the peripheral.
According to REG_CONF10(0) configuration reg-
ister bit, POL, the firing pulses polarity must be
set.
A programmable interrupt may be generated in
four different ways:
1) no Interrupt;
2) Interrupt on the rising edge of the signal MAIN1
(INT_R)
3)Interrupt on the falling edge of the signal MAIN2
(INT_F)
4) Interrupt on both the edges of the signal MAIN1
5) Interrupt on rising edge of first pulse after T1
(INT_P)
If UTP is 0, TROUT signal remains at 0 (or 1, if
POL=1), however after the time T1, the interrupt
INT_P is generated.
The Interrupt sources described above are always
active;
REG_CONF0(5:3) bits, INTSL (see Table 4.1).
CKLM
they
T1 =TRIAC_COUNT* T
master clock period and N the Pres-
can
Ti/2 = T
be
CLKM
masked
CKLM
*UTP
* (N+1)
through