DS21552L+ Maxim Integrated Products, DS21552L+ Datasheet
DS21552L+
Specifications of DS21552L+
Related parts for DS21552L+
DS21552L+ Summary of contents
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FEATURES § Complete DS1/ISDN–PRI/J1 transceiver functionality § Long and Short haul LIU § Crystal–less jitter attenuator § Generates DSX–1 and CSU line build-outs § HDLC controller with 64-byte buffers Configurable for FDL or DS0 operation § Dual two–frame elastic ...
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TABLE OF CONTENTS 1. LIST OF FIGURES .........................................................................................................................5 2. LIST OF TABLES ...........................................................................................................................6 3. INTRODUCTION............................................................................................................................7 3.1 FUNCTIONAL DESCRIPTION..............................................................................................8 3.2 DOCUMENT REVISION HISTORY....................................................................................10 4. PIN DESCRIPTION ......................................................................................................................11 4.1 PIN FUNCTION DESCRIPTION..........................................................................................17 4.1.1 Transmit Side Pins ........................................................................................................17 4.1.2 Receive Side Pins ..........................................................................................................20 ...
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SIGNALING OPERATION..........................................................................................................58 10.1 PROCESSOR-BASED SIGNALING ....................................................................................58 10.2 HARDWARD-BASED SIGNALING ...................................................................................60 10.2.1 Receive Side.................................................................................................................60 10.2.2 Transmit Side...............................................................................................................61 11. PER-CHANNEL CODE (IDLE) GENERATION ......................................................................61 11.1 TRANSMIT SIDE CODE GENERATION ...........................................................................62 11.1.1 Fixed Per-Channel Idle Code Insertion ......................................................................62 11.1.2 Unique Per-Channel Idle ...
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LINE INTERFACE FUNCTION .................................................................................................85 16.1 RECEIVE CLOCK AND DATA RECOVERY ....................................................................85 16.2 TRANSMIT WAVE SHAPING AND LINE DRIVING.......................................................86 16.3 JITTER ATTNUATOR..........................................................................................................86 16.4 PROTECTED INTERFACES................................................................................................92 16.5 RECEIVE MONITOR MODE...............................................................................................95 17. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION ............96 18. TRANSMIT ...
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LIST OF FIGURES Figure 3-1 SCT BLOCK DIAGRAM.........................................................................................................9 Figure 16-1 EXTERNAL ANALOG CONNECTIONS ..........................................................................87 Figure 16-2 OPTIONAL CRYSTAL CONNECTIONS ..........................................................................88 Figure 16-3 TRANSMIT WAVEFORM TEMPLANE............................................................................89 Figure 16-4 JITTER TOLERANCE .........................................................................................................91 Figure 16-5 JITTER ATTENUATION ....................................................................................................91 Figure 16-6 PROTECTED INTERFACE ...
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LIST OF TABLES Table 4-1 PIN DESCRIPTION SORTED BY PIN NUMBER................................................................11 Table 4-2 PIN DESCRIPTION SORTED BY PIN SYMBOL ................................................................14 Table 5-1 REGISTER MAP SORTED BY ADDRESS...........................................................................29 Table 6-1 DEVICE ID BIT MAP .............................................................................................................33 Table 6-2 OUTPUT PIN TEST ...
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INTRODUCTION The DS21352/552 are 3.3V/5V superset versions of the popular DS2152 T1 single-chip transceiver offering the new features listed below. All of the original features of the DS2152 have been retained and software created for the original devices is ...
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FUNCTIONAL DESCRIPTION The analog AMI/B8ZS waveform off of the T1 line is transformer coupled into the RRING and RTIP pins of the DS21352/552. The device recovers clock and data from the analog signal and passes it through the jitter ...
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Figure 3-1 SCT BLOCK DIAGRAM CI RPOSI RCLKI RNEGI RNEGO RCLKO RPOSO 8XCLK MHz XTALD MCLK Payload Loopback Framer Loopback Remote Loopback Jitter Attenuator 12.352 Either transmit or receive path Local Loopback Receive Line I/F Clock / Data Recovery 9 ...
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DOCUMENT REVISION HISTORY Revision 12-10-98 Initial Release 12-18-98 Add LIUODO (LIU Open Drain Output) to CCR7.0 Add CDIG (Customer Disconnect Indication Generator) to CCR7.1 Add LIUSI (Line Interface Unit Synchronization Interface) to CCR7.2 Correct IBO register bit functions order ...
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PIN DESCRIPTION Table 4-1 PIN DESCRIPTION SORTED BY PIN NUMBER PIN SYMBOL 1 RCHBLK 2 JTMS 3 8MCLK 4 JTCLK 5 JTRST 6 RCL 7 JTDI JTDO 11 BTS 12 LIUC 13 8XCLK 14 ...
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TDATA 51 TSYSCLK 52 TSSYNC 53 TCHCLK MUX 56 D0/AD0 57 D1/AD1 58 D2/AD2 59 D3/AD3 60 DVSS 61 DVDD 62 D4/AD4 63 D5/AD5 64 D6/AD6 65 D7/AD7 ...
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Table 4-1 PIN DESCRIPTION SORTED BY PIN SYMBOL PIN SYMBOL 3 8MCLK 13 8XCLK ALE (AS)/A7 11 BTS CS* 56 ...
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RCLKI 89 RCLKO 74 RD*(DS*) 85 RDATA 97 RFSYNC 79 RLCLK 78 RLINK 99 RLOS/LOTC 96 RMSYNC 87 RNEGI 90 RNEGO 86 RPOSI 91 RPOSO 17 RRING 95 RSER 94 RSIG 93 RSIGF 98 RSYNC 100 RSYSCLK 16 RTIP ...
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PIN FUNCTION DESCRIPTION 4.1.1 TRANSMIT SIDE PINS Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 1.544 MHz primary clock. Used to clock data through the transmit side formatter. Signal Name: TSER Signal Description: Transmit Serial Data ...
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TRANSMIT SIDE PINS (cont.) Signal Name: TLINK Signal Description: Transmit Link Data Signal Type: Input If enabled via TCR1.2, this pin will be sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) ...
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TRANSMIT SIDE PINS (cont.) Signal Name: TNEGO Signal Description: Transmit Negative Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit side formatter. This pin is normally tied to ...
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RECEIVE SIDE PINS Signal Name: RLINK Signal Description: Receive Link Data Signal Type: Output Updated with either FDL data (ESF bits (D4 bits (ZBTSI) one RCLK before the start of a frame. See Section 20 ...
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RECEIVE SIDE PINS (cont.) Signal Name: RFSYNC Signal Description: Receive Frame Sync Signal Type: Output An extracted 8 kHz pulse, one RCLK wide, is output at this pin which identifies frame boundaries. Signal Name: RMSYNC Signal Description: Receive Multiframe ...
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Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI. Signal Name: RNEGO Signal Description: Receive Negative Data Input Signal Type: Output Updated on the rising edge of ...
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PARALLEL CONTROL PORT PINS Signal Name: INT* Signal Description: Interrupt Signal Type: Output Flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2 and the HDLC Status Register. Active low, open drain ...
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PARALLEL CONTROL PORT PINS (cont.) Signal Name: CS* Signal Description: Chip Select Signal Type: Input Must be low to read or write to the device. CS active low signal. Signal Name: ALE(AS)/A7 Signal Description: Address Latch Enable(Address ...
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JTAG TEST ACCESS PORT PINS Signal Name: JTRST Signal Description: IEEE 1149.1 Test Reset Signal Type: Input If FMS = 1: JTAG functionality is not available and JTRST is held LOW internally. If FMS = 0: JTAG functionality is ...
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LINE INTERFACE PINS Signal Name: MCLK Signal Description: Master Clock Input Signal Type: Input A 1.544 MHz (50 ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and ...
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SUPPLY PINS Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 5.0 volts +/-5% (DS21552) or 3.3 volts +/-5% (DS21352). Should be tied to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive ...
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PARALLEL PORT The SCT is controlled via either a non–multiplexed (MUX = multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The SCT can operate with either Intel or Motorola bus timing configurations. If ...
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ADDRESS R Multiframe Out of Sync Count Receive FDL Register 29 R/W Receive FDL Match 1 2A R/W Receive FDL Match 2 2B R/W Receive Control 1 2C R/W Receive Control 2 2D R/W Receive ...
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R/W Receive Channel 19 5B R/W Receive Channel 20 5C R/W Receive Channel 21 5D R/W Receive Channel 22 5E R/W Receive Channel 23 5F R/W Receive Channel Receive Signaling Receive Signaling 2 ...
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R/W Receive Channel 16 90 R/W Receive HDLC DS0 Control Register 1 91 R/W Receive HDLC DS0 Control Register 2 92 R/W Transmit HDLC DS0 Control Register 1 93 R/W Transmit HDLC DS0 Control Register 2 94 R/W Interleave ...
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Bit 6 IDR.6 Bit 6. Bit 5 IDR.5 Bit 5. Bit 4 IDR.4 Bit 4. ID3 IDR.3 Chip Revision Bit 3. MSB of a decimal code that represents the chip revision. ID2 IDR.1 Chip Revision Bit ...
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Table 6-1 DEVICE ID BIT MAP SCT T1/E1 DS2152 0 DS21352 0 DS21552 0 DS2154 1 DS21354 1 DS21554 1 The lower four bits of the IDR are used to display the die revision of the chip. RCR1: RECEIVE CONTROL ...
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RCR2: RECEIVE CONTROL REGISTER 2 (Address=2C Hex) (MSB) RCS RZBTSI RSDW SYMBOL POSITION RCS RCR2.7 RZBTSI RCR2.6 RSDW RCR2.5 RSM RCR2.4 RSIO RCR2.3 RD4YM RCR2.2 FSBE RCR2.1 MOSCRF RCR2.0 RSM RSIO NAME AND DESCRIPTION Receive Code Select idle ...
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TCR1: TRANSMIT CONTROL REGISTER 1 (Address=35 Hex) (MSB) LOTCMC TFPT SYMBOL POSITION LOTCMC TCR1.7 TFPT TCR1.6 TCPT TCR1.5 TSSE TCR1.4 GB7S TCR1.3 TFDLS TCR1.2 TBL TCR1.1 TYEL TCR1.0 NOTE: For a description of how the bits in TCR1 affect the ...
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TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex) (MSB) TEST1 TEST0 TZBTSI SYMBOL POSITION NAME AND DESCRIPTION TEST1 TCR2.7 Test Mode Bit 1 for Output Pins. See Table 6-2.. TEST0 TCR2.6 Test Mode Bit 0 for Output Pins. See Table 6-2. ...
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CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex) (MSB) TESE ODF SYMBOL POSITION TESE CCR1.7 ODF CCR1.6 RSAO CCR1.5 TSCLKM CCR1.4 RSCLKM CCR1.3 RESE CCR1.2 PLB CCR1.1 FLB CCR1.0 6.3 PAYLOAD LOOPBACK Payload Loopback When CCR1.1 is set to a one, ...
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All receive side signals will take on timing synchronous with TCLK instead of RCLKI. Please note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will cause an unstable condition. CCR2: COMMON ...
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Loss of Transmit Clock (LOTC) RSMS CCR3.4 RSYNC Multiframe Skip Control. Useful in framing format conversions from D4 to ESF. This function is not available when the receive side elastic store is enabled RSYNC will output ...
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PULSE DENSITY ENFORCER The Framer always examines both the transmit and receive data streams for violations of the following rules which are required by ANSI T1.403: – no more than 15 consecutive zeros – at least N ones in ...
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CCR4: COMMON CONTROL REGISTER 4 (Address=11 Hex) (MSB) RSRE RPCSI RFSA1 SYMBOL POSITION RSRE CCR4.7 RPCSI CCR4.6 RFSA1 CCR4.5 RFE CCR4.4 RFF CCR4.3 THSE CCR4.2 TPCSI CCR4.1 TIRFS CCR4.0 RFE RFF NAME AND DESCRIPTION Receive Side Signaling Re–Insertion Enable. See ...
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CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex) (MSB) TJC LLB LIAIS SYMBOL POSITION TJC CCR5.7 LLB CCR5.6 LIAIS CCR5.5 TCM4 CCR5.4 TCM3 CCR5.3 TCM2 CCR5.2 TCM1 CCR5.1 TCM0 CCR5.0 TCM4 TCM3 NAME AND DESCRIPTION Transmit Japanese CRC6 Enable ...
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CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex) (MSB) RJC RESA SYMBOL POSITION RJC CCR6.7 RESA CCR6.6 TESA CCR6.5 RCM4 CCR6.4 RCM3 CCR6.3 RCM2 CCR6.2 RCM1 CCR6.1 RCM0 CCR6.0 TESA RCM4 RCM3 NAME AND DESCRIPTION Receive Japanese CRC6 Enable ...
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CCR7: COMMON CONTROL REGISTER 7 (Address=0A Hex) (MSB) LIRST RLB SYMBOL POSITION LIRST CCR7.7 RLB CCR7.6 RESR CCR7.5 TESR CCR7.4 - CCR7.3 LIUSI CCR7.2 CDIG CCR7.1 LIUODO CCR7.0 6.6 REMOTE LOOPBACK When CCR7.6 is set to a one, the DS21352/552 ...
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STATUS AND INFORMATION REGISTERS There is a set of nine registers that contain information on the current real time status of the device, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Registers (RIR1/RIR2/RIR3) and ...
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RIR1: RECEIVE INFORMATION REGISTER 1 (Address=22 Hex) (MSB) COFA 8ZD SYMBOL POSITION COFA RIR1.7 8ZD RIR1.6 16ZD RIR1.5 RESF RIR1.4 RESE RIR1.3 SEFE RIR1.2 B8ZS RIR1.1 FBE RIR1.0 RIR2: RECEIVE INFORMATION REGISTER 2 (Address=31 Hex) (MSB) RLOSC LRCLC TESF SYMBOL ...
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LORC RIR3.4 Loss of Receive Clock. Set when the RCLKI pin has not transitioned for at least max). FRCL RIR3.3 Framer Receive Carrier Loss. Set when ...
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SR1: STATUS REGISTER 1 (Address=20 Hex) (MSB) LUP LDN LOTC SYMBOL POSITION LUP SR1.7 LDN SR1.6 LOTC SR1.5 RSLIP SR1.4 RBL SR1.3 RYEL SR1.2 LRCL SR1.1 RLOS SR1.0 RSLIP RBL NAME AND DESCRIPTION Loop Up Code Detected. Set when the ...
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Table 7-2 ALARM CRITERIA ALARM Blue Alarm (AIS) (see note 1 below) Yellow Alarm (RAI bit 2 mode(RCR2.2= 12th F–bit mode (RCR2.2=1; this mode is also referred to as the “Japanese Yellow Alarm”) 3. ESF mode ...
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SR2: STATUS REGISTER 2 (Address=21 Hex) (MSB) RMF TMF SYMBOL POSITION RMF SR2.7 TMF SR2.6 SEC SR2.5 RFDL SR2.4 TFDL SR2.3 RMTCH SR2.2 RAF SR2.1 RSC SR2.0 SEC RFDL TFDL NAME AND DESCRIPTION Receive Multiframe. Set on receive multiframe boundaries. ...
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IMR1: INTERRUPT MASK REGISTER 1 (Address=7F Hex) (MSB) LUP LDN LOTC SYMBOL POSITION LUP IMR1.7 LDN IMR1.6 LOTC IMR1.5 SLIP IMR1.4 RBL IMR1.3 RYEL IMR1.2 LRCL IMR1.1 RLOS IMR1.0 SLIP RBL NAME AND DESCRIPTION Loop Up Code Detected ...
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IMR2: INTERRUPT MASK REGISTER 2 (Address=6F Hex) (MSB) RMF TMF SYMBOL POSITION RMF IMR2.7 TMF IMR2.6 SEC IMR2.5 RFDL IMR2.4 TFDL IMR2.3 RMTCH IMR2.2 RAF IMR2.1 RSC IMR2.0 8. ERROR COUNT REGISTERS There are a set of three counters that ...
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LINE CODE VIOLATION COUNT REGISTER (LCVCR) Line Code Violation Count Register 1 (LCVCR1) is the most significant word and LCVCR2 is the least significant word of a 16–bit counter that records code violations (CVs). CVs are defined as Bipolar ...
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PATH CODE VIOLATION COUNT REGISTER (PCVCR) When the receive side of a framer is set to operate in the ESF framing mode (CCR2.3=1), PCVCR will automatically be set as a 12–bit counter that will record errors in the CRC6 ...
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Multiframes Out Of Sync Count Register (MOSCR) Normally the MOSCR is used to count the number of multiframes that the receive synchronizer is out of sync (RCR2.0=1). This number is useful in ESF applications needing to measure the parameters ...
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DS0 MONITORING FUNCTION The device has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which ...
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TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address=1A Hex) (MSB SYMBOL POSITION B1 TDS0M.7 B2 TDS0M.6 B3 TDS0M.5 B4 TDS0M.4 B5 TDS0M.3 B6 TDS0M.2 B7 TDS0M.1 B8 TDS0M.0 CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex) [repeated here from section 6 ...
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B5 RDS0M.3 B6 RDS0M.2 B7 RDS0M.1 B8 RDS0M.0 10. SIGNALING OPERATION Processor based (i.e., software based) signaling access and hardware based access are available. Processor based access and hardware based access can be used simultaneously if necessary. The processor based ...
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RS1 TO RS12: RECEIVE SIGNALING REGISTERS (Address= Hex) (MSB) A(8) A(7) A(6) A(16) A(15) A(14) A(24) A(23) A(22) B(8) B(7) B(6) B(16) B(15) B(14) B(24) B(23) B(22) A/C(8) A/C(7) A/C(6) A/C(16) A/C(15) A/C(14) A/C(24) A/C(23) A/C(22) B/D(8) B/D(7) ...
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TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address= Hex (MSB) A(8) A(7) A(6) A(16) A(15) A(14) A(24) A(23) A(22) B(8) B(7) B(6) B(16) B(15) B(14) B(24) B(23) B(22) A/C(8) A/C(7) A/C(6) A/C(16) A/C(15) A/C(14) A/C(24) A/C(23) A/C(22) B/D(8) B/D(7) ...
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In this mode, the elastic store must be enabled however the backplane clock can be either 1.544 MHz or 2.048 MHz. If the signaling re–insertion mode is enabled, the user can control which channels have signaling re– insertion ...
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TRANSMIT SIDE CODE GENERATION In the transmit direction there are two methods by which channel data from the backplane can be overwritten with data generated by the framer. The first method which is covered in Section 11.1 was a ...
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TC1 TO TC24: TRANSMIT CHANNEL REGISTERS (Address= and Hex) (for brevity, only channel one is shown; see Table 5-1 for other register address) (MSB SYMBOL POSITION C7 TC1.7 C0 TC1.0 TCC1/TCC2/TCC3: TRANSMIT ...
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FIXED PER-CHANNEL IDLE CODE INSERTION The first method on the receive side involves using the Receive Mark Registers (RMR1/2/3) to determine which of the 24 T1 channels should be overwritten with either a 7Fh idle code or with a ...
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RCC1/RCC2/RCC3: RECEIVE CHANNEL CONTROL REGISTER (ADDRESS= Hex) (MSB) CH8 CH7 CH6 CH16 CH15 CH14 CH24 CH23 CH22 SYMBOL POSITION CH24 RCC3.7 CH1 RCC1.0 12. PER–CHANNEL LOOPBACK The Transmit Idle Registers (TIRs) have an alternate function that allows them ...
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ELASTIC STORES OPERATION The device contains dual two–frame (386 bits) elastic stores, one for the receive direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert the ...
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TRANSMIT SIDE The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic store is enabled via CCR1.7. A 1.544 MHz (CCR1.4=0) or 2.048 MHz (CCR1.4=1) clock can be applied to the ...
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TBOC and TDC1 cannot exist without corrupting the data in the FDL. See Table 15-1 for configuring the transmit HDLC controller. Table 15-1 TRANSMIT HDLC CONFIGURATION Function DS0(s) FDL Disable Note that the BOC controller is ...
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Firmware, which can /Telecom/t1_e1_tools.html), was developed to implement the FDL. incorporates the LAPD protocol and can be used with any of the 51/52/352/552 SCTs. The code for the DS2152 can be used with the 52/352/552 SCTs. 15.3 HDLC AND BOC ...
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Table 15-2 HDLC/BOC CONTROLLER REGISTERS NAME HDLC Control Register (HCR) HDLC Status Register (HSR) HDLC Interrupt Mask Register (HIMR) Receive HDLC Register (RHIR) Receive BOC Register (RBOC) Receive HDLC FIFO Register (RHFR) Receive HDLC DS0 Control Register 1 (RDC1) Receive ...
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Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware interrupt via the INT* output pin. Each of the events in the HSR can be either masked or unmasked from the interrupt ...
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TRANSMIT AN HDLC MESSAGE 1) Make sure HDLC controller is done sending any previous messages and is current sending flags by checking that the FIFO is empty by reading the TEMPTY status bit in the TPRM register. 2) Enable ...
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RPE HSR.6 RPS HSR.5 RHALF HSR.4 RNE HSR.3 THALF HSR.2 TNF HSR.1 TMEND HSR.0 NOTE: The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read. Receive Packet End. Set when the HDLC controller detects either ...
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HIMR: HDLC INTERRUPT MASK REGISTER (Address=02 Hex) (MSB) RBOC RPE SYMBOL POSITION RBOC HIMR.7 RPE HIMR.6 RPS HIMR.5 RHALF HIMR.4 RNE HIMR.3 THALF HIMR.2 TNF HIMR.1 TMEND FIMR.0 RPS RHALF RNE NAME AND DESCRIPTION Receive BOC Detector Change of State. ...
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RHIR: RECEIVE HDLC INFORMATION REGISTER (Address=03 Hex) (MSB) RABT RCRCE ROVR SYMBOL POSITION RABT RHIR.7 RCRCE RHIR.6 ROVR RHIR.5 RVM RHIR.4 REMPTY RHIR.3 POK RHIR.2 CBYTE RHIR.1 OBYTE RHIR.0 NOTE: The RABT, RCRCE, ROVR, and RVM bits are latched and ...
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RBOC: RECEIVE BIT ORIENTED CODE REGISTER (Address=04 Hex) (MSB) LBD BD BOC5 SYMBOL POSITION LBD RBOC.7 BD RBOC.6 BOC5 RBOC.5 BOC4 RBOC.4 BOC3 RBOC.3 BOC2 RBOC.2 BOC1 RBOC.1 BOC0 RBOC.0 NOTE: 1. The LBD bit is latched and will be ...
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RHFR: RECEIVE HDLC FIFO (Address=05 Hex) (MSB) RHFR7 RHFR6 RHFR5 SYMBOL POSITION RHFR7 RHFR.7 RHFR6 RHFR.6 RHFR5 RHFR.5 RHFR4 RHFR.4 RHFR3 RHFR.3 RHFR2 RHFR.2 RHFR1 RHFR.1 RHFR0 RHFR.0 THIR: TRANSMIT HDLC INFORMATION (Address=06 Hex) (MSB) – – SYMBOL POSITION – ...
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BOC5 TBOC.5 BOC4 TBOC.4 BOC3 TBOC.3 BOC2 TBOC.2 BOC1 TBOC.1 BOC0 TBOC.0 THFR: TRANSMIT HDLC FIFO (Address=08 Hex) (MSB) THFR7 THFR6 THFR5 SYMBOL POSITION THFR7 THFR.7 THFR6 THFR.6 THFR5 THFR.5 THFR4 THFR.4 THFR3 THFR.3 THFR2 THFR.2 THFR1 THFR.1 THFR0 THFR.0 ...
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RD1 RDC1.1 DS0 Channel Select Bit 1. RD0 RDC1.0 DS0 Channel Select Bit 0. LSB of the DS0 channel select 137 ...
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RDC2: RECEIVE HDLC DS0 CONTROL REGISTER 2 (Address=91 Hex) (MSB) RDB8 RDB7 RDB6 SYMBOL POSITION RDB8 RDC2.7 RDB7 RDC2.6 RDB6 RDC2.5 RDB5 RDC2.4 RDB4 RDC2.3 RDB3 RDC2.2 RDB2 RDC2.1 RDB1 RDC2.0 RDB5 RDB4 NAME AND DESCRIPTION DS0 Bit 8 Suppress ...
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TDC1: TRANSMIT HDLC DS0 CONTROL REGISTER 1 (Address=92 Hex) (MSB) TDS0E - TDS0M SYMBOL POSITION TDS0E TDC1.7 - TDC1.6 TDS0M TDC1.5 TD4 TDC1.4 TD3 TDC1.3 TD2 TDC1.2 TD1 TDC1.1 TD0 TDC1.0 TD4 TD3 NAME AND DESCRIPTION HDLC DS0 Enable. 0 ...
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TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 (Address=93 Hex) (MSB) TDB8 TDB7 TDB6 SYMBOL POSITION TDB8 TDC2.7 TDB7 TDC2.6 TDB6 TDC2.5 TDB5 TDC2.4 TDB4 TDC2.3 TDB3 TDC2.2 TDB2 TDC2.1 TDB1 TDC2.0 15.4 LEGACY FDL SUPPORT 15.4.1 OVERVIEW In order to ...
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The framer also contains a zero destuffer which is controlled via the CCR2.0 bit. In both ANSI T1.403 and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no more than 5 ...
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TRANSMIT SECTION The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a ...
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LINE INTERFACE FUNCTION The line interface function in the DS21352/552 contains three sections; (1) the receiver which handles clock and data recovery, (2) the transmitter which waveshapes and drives the T1 line, and (3) the jitter attenuator. Each of ...
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TRANSMIT WAVE SHAPING AND LINE DRIVING The DS21352/552 uses a set of laser–trimmed delay lines along with a precision Digital–to–Analog Converter (DAC) to create the waveforms that are transmitted onto the T1 line. The waveforms created by the DS21352/552 ...
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Figure 16-1 EXTERNAL ANALOG CONNECTIONS T1 Transmit Line (see table below) T1 Receive Line Table 16-2 TRANSMIT TRANSFORMER SELECTION DEVICE DS21552 DS21352 See separate application note on line interface design criteria for full details. NOTES: 1. Resistor values are +/-1%. ...
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Figure 16-2 OPTIONAL CRYSTAL CONNECTIONS DS21352/552 XTALD MCLK NOTES and C2 should lower than two times the nominal loading capacitance of the crystal to adjust for the input capacitance of the DS21352/552. 1.544MHz C1 C2 ...
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Figure 16-3 TRANSMIT WAVEFORM TEMPLATE 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 T1.102/87, T1.403, -0 119 (O ct. 79), & I.431 Tem plate -0.3 -0.4 -0.5 -500 -400 -300 -200 -100 ...
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Table 16-4 PULSE TEMPLATE CORNER POINTS TIME (ns) UI -500 -0.77 -255 -0.39 -175 -0.27 -175 -.027 -150 -0.23 -150 -0.23 -100 -75 -0.12 0 0.00 100 0.15 150 0.23 150 0.23 175 0.27 225 0.35 300 0.46 430 0.66 ...
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Figure 16-4 JITTER TOLERANCE 1K 100 olerance T R 62411 ( Figure 16-5 JITTER ATTENUATION ...
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PROTECTED INTERFACES In certain applications, such as connecting to the PSTN required that the network interface be protected from and resistant to certain electrical conditions. These conditions are divided into two categories, surge and power line cross. ...
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Figure 16-6 PROTECTED INTERFACE EXAMPLE FOR THE DS21552 R1 Fuse Transmit R2 Line Fuse R3 Fuse Receive R4 Line Fuse Note: The 68uf cap is required to maintain VDD during a transient event. COMPONET D1 – D4 Schottky Diode, International ...
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Figure 16-7 PROTECTED INTERFACE EXAMPLE FOR THE DS21352 2:1 Fuse Transmit Line Fuse X1 1:1 Fuse Receive Line Fuse X2 Note: The 68uf cap is required to maintain VDD levels during a transient event. COMPONET D1 – D4 Schottky Diode, ...
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RECEIVE MONITOR MODE When connecting to a monitor port a large resistive loss is incurred due to the voltage divider between the T1 line termination resistors (Rt) and the monitor port isolation resistors (Rm) as shown below. The Rm ...
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PROGRAMMABLE IN–BAND LOOP CODE GENERATION AND DETECTION Each framer in the DS21352/552 has the ability to generate and detect a repeating bit pattern that is from one to eight bits in length. To transmit a pattern, the user will ...
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Table 17-1 TRANSMIT CODE LENGTH TC1 TC0 Table 17-2 RECEIVE CODE LENGTH RUP2/ RDN2 TCD: TRANSMIT CODE DEFINITION REGISTER (Address=13 Hex) (MSB SYMBOL POSITION NAME AND ...
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RUPCD: RECEIVE UP CODE DEFINITION REGISTER (Address=14 Hex) (MSB SYMBOL POSITION C7 RUPCD.7 C6 RUPCD.6 C5 RUPCD.5 C4 RUPCD.4 C3 RUPCD.3 C2 RUPCD.2 C1 RUPCD.1 C0 RUPCD.0 RDNCD: RECEIVE DOWN CODE DEFINITION REGISTER (Address=15 Hex) (MSB ...
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TRANSMIT TRANSPARENCY Each of the 24 T1 channels in the transmit direction of the framer can be either forced to be transparent or in other words, can be forced to stop Bit 7 Stuffing and/or Robbed Signaling from overwriting ...
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The DS21352/552 are enhanced versions of the DS2152 and are backward pin-compatible. The JTAG feature uses pins that had no function in the DS2152. When using the JTAG feature, be sure FMS (pin 76) is tied LOW enabling the newly ...
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TAP CONTROLLER STATE MACHINE The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 19-1. TEST-LOGIC-RESET Upon power up, the TAP Controller will be in ...
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SELECT-IR-SCAN All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and will initiate a scan sequence for the ...
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Figure 19-2 TAP CONTROLLER STATE DIAGRAM Test Logic 1 Reset 0 1 Run Test/ 0 Idle 19.3 INSTRUCTION REGISTER The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When ...
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Table 19-1 INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE Instruction SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE SAMPLE/PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification. functions. The digital I/Os of the device can be sampled at the boundary scan ...
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IDCODE When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code will be loaded into the identification register on the rising edge of JTCLK following entry into the Capture-DR ...
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IDENTIFICATION REGISTER The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic- Reset state. See Table 19-2. Table 19-3 ...
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– ...
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RFSYNC 6 – RSYNC.cntl 5 98 RSYNC 4 99 RLOS/LOTC 3 100 RSYSCLK O – RSYNC an input 1 = RSYNC an output I 106 of 137 ...
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INTERLEAVED PCM BUS OPERATION In many architectures, the outputs of individual framers are combined into higher speed serial buses to simplify transport across the system. The DS21352/552 can be configured to allow data and signaling buses to be multiplexed ...
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Table 20-1 MASTER DEVICE BUS SELECT MSEL1 MSEL0 Figure 20-1 IBO BASIC CONFIGURATION USING 4 SCTS CI RSYSCLK TSYSCLK RSYNC TSSYNC MASTER RSIG SCT TSIG TSER CO RSER CI RSYSCLK TSYSCLK RSYNC ...
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CHANNEL INTERLEAVE In channel interleave mode data is output to the PCM Data Out bus one channel at a time from each of the connected SCTs until all channels of frame n from all each SCT has been place ...
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Figure 21-2 RECEIVE SIDE ESF TIMING FRAME# 1 RSYNC RFSYNC 2 RSYNC 3 RSYNC 4 RLCLK 5 RLINK 6 TLCLK 7 TLINK Notes: 1. RSYNC in frame mode (RCR2 and double wide ...
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Figure 21-3 RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled) RCLK CHANNEL 23 RSER RSYNC RFSYNC CHANNEL RSIG RCHCLK RCHBLK 1 RLCLK RLINK 2 Notes: 1. RCHBLK is programmed to block channel 24 2. Shown is RLINK/RLCLK ...
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Figure 21-5 RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) RSYSCLK CHANNEL 31 1 RSER 2 RSYNC RMSYNC 3 RSYNC A RSIG RCHCLK 4 RCHBLK Notes: 1. RSER data in channels 13, 17, 21, 25, ...
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Figure 21-6 RECEIVE SIDE INTERLEAVE BUS OPERATION, BYTE MODE RSYNC 1 RSER FR1 CH32 1 FR1 CH32 RSIG 2 FR2 CH32 FR3 CH32 FR0 CH1 RSER 2 RSIG FR2 CH32 FR3 CH32 FR0 CH1 RSYSCLK 3 RSYNC FRAMER 3, CHANNEL ...
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Figure 21-7 RECEIVE SIDE INTERLEAVE BUS OPERATION, FRAME MODE RSYNC 1 RSER FR1 CH1-32 RSIG FR1 CH1-32 2 RSER FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 2 ...
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Figure 21-8 TRANSMIT SIDE D4 TIMING FRAME TSYNC TSSYNC 2 TSYNC 3 TSYNC TLCLK 4 TLINK Notes: 1. TSYNC in the frame mode (TCR2 and double-wide frame sync is not enabled (TCR2 ...
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Figure 21-9 TRANSMIT SIDE ESF TIMING FRAME TSYNC TSSYNC 2 TSYNC 3 TSYNC 4 TLCLK TLINK 5 TLCLK 6 TLINK Notes: 1. TSYNC in frame mode (TCR2 and double-wide frame sync ...
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Figure 21-10 TRANSMIT SIDE BOUNDARY TIMING (with elastic store disabled) TCLK TSER LSB F MSB 1 TSYNC 2 TSYNC TSIG D/B TCHCLK 3 TCHBLK TLCLK 4 TLINK Notes: 1. TSYNC is in the output mode (TCR2 TSYNC ...
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Figure 21-12 TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) TSYSCLK CHANNEL 31 1 TSER TSSYNC CHANNEL 31 A TSIG TCHCLK 2,3 TCHBLK Notes: 1. TSER data in channels 13, 17, 21, 25, and 29 ...
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Figure 21-13 TRANSMIT SIDE INTERLEAVE BUS OPERATION, BYTE MODE TSSYNC 1 FR1 CH32 TSER 1 FR1 CH32 TSIG 2 FR2 CH32 FR3 CH32 FR0 CH1 TSER 2 FR2 CH32 FR3 CH32 FR0 CH1 TSIG TSYSCLK 3 TSSYNC FRAMER 3, CHANNEL ...
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Figure 21-14 TRANSMIT INTERLEAVE BUS OPERATION, FRAME MODE TSSYNC 1 TSER FR1 CH1-32 1 FR1 CH1-32 TSIG 2 TSER FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 2 ...
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RECEIVE AND TRANSMIT DATA FLOW DIAGRAMS Figure 22-1 RECEIVE DATA FLOW RSYNC RMR1 to RMR3 RCBR1 to RCBR3 Per Channel Signaling Re-Insert Enable (CCR4.6) Signaling Re-insertion enable (CCR4.7) RNEGI RPOSI B8ZS Decoder 0 1 Receive Mark Code Insertion 0 ...
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Figure 22-2 TRANSMIT DATA FLOW TCBR1/2/3 CCR4.1 DS0 insertion enable (TDC1.7) DS2152 TRANSMIT DATA FLOW Figure 15.11 0 TCD1 4:0 TCHBLK 1 TDC1.5 TIR Function Select (CCR4.0) 0 TIDR RSER (note#1) 1 Software Signaling Enable (TCR1.4) TTR1 to TTR3 Global ...
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OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature for DS21352L/DS21552L Operating Temperature for DS21352LN/DS21552LN Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these ...
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AC TIMING PARAMETERS AND DIAGRAMS 24.1 MULTIPLEXED BUS AC CHARACTERISTICS AC CHARACTERISTICS – MULTIPLEXED PARALLEL PORT (MUX = 1) [See Figure 24-1 to Figure 24-3] PARAMETER SYMBOL Cycle Time Pulse Width, DS low or RD* high Pulse Width, DS ...
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Figure 24-1 INTEL BUS READ TIMING (BTS=0 / MUX = 1) ALE t ASD WR* RD* PW CS* AD0-AD7 Figure 24-2 INTEL BUS WRITE TIMING (BTS=0 / MUX=1) ALE t ASD RD* t ASD WR* PW CS* AD0-AD7 t CYC ...
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Figure 24-3 MOTOROLA BUS TIMING (BTS = 1 / MUX = ASD R/W* AD0-AD7 (read) CS* AD0-AD7 (write) PW ASH t ASED t RWS t ASL t AHL ASL t AHL ...
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NON-MULTIPLEXED BUS AC CHARACTERISTICS AC CHARACTERISTICS – NON-MULTIPLEXED PARALLEL PORT (MUX = 0) [See Figure 24-4 to Figure 24-7] PARAMETER SYMBOL Set Up Time for A0 to A7, Valid to CS* Active Set Up Time for CS* Active to ...
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Figure 24-4 INTEL BUS READ TIMING (BTS=0 / MUX= WR* t1 CS* 0ns min. RD* Figure 24-5 INTEL BUS WRITE TIMING (BTS=0 / MUX= RD* t1 CS* 0ns ...
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Figure 24-6 MOTOROLA BUS READ TIMING (BTS=1 / MUX= R/W* t1 CS* 0ns min. DS* Figure 24-7 MOTOROLA BUS WRITE TIMING (BTS=1 / MUX= R/W* t1 CS* 0ns ...
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RECEIVE SIDE AC CHARACTERISTICS AC CHARACTERISTICS – RECEIVE SIDE [See Figure 24-8 to Figure 24-10] PARAMETER RCLKO Period RCLKO Pulse Width RCLKO Pulse Width RCLKI Period RCLKI Pulse Width RSYSCLK Period RSYSCLK Pulse Width RSYNC Set Up to RSYSCLK ...
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RCLK t D1 RSER / RDATA / RSIG RCHCLK RCHBLK RFSYNC / RMSYNC 1 RSYNC 2 RLCLK RLINK Notes: 1. RSYNC is in the output mode (RCR2.3 = 0). 2. Shown is RLINK/RLCLK in the ESF framing mode 3. No ...
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Figure 24.9 RECEIVE SIDE TIMING, ELASTIC STORE ENABLED t R RSYSCLK t D3 RSER / RSIG RCHCLK RCHBLK RMSYNC / CO 1 RSYNC 2 RSYNC CI Notes: 1. RSYNC is in the output mode (RCR2 RSYNC is ...
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Figure 24-10 RECEIVE LINE INTERFACE TIMING RCLKO t DD RPOSO, RNEGO t R RCLKI RPOSI, RNEGI 133 of 137 ...
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TRANSMIT AC CHARACTERISTICS AC CHARACTERISTICS – TRANSMIT SIDE [See Figure 24-11 to Figure 24-13] PARAMETER TCLK Period TCLK Pulse Width TCLKI Period TCLKI Pulse Width TSYSCLK Period TSYSCLK Pulse Width TSYNC or TSSYNC Set Up to TCLK or TSYSCLK ...
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Figure 24-11 TRANSMIT SIDE TIMING t R TCLK TESO TSER / TSIG / TDATA t D2 TCHCLK TCHBLK 1 TSYNC 2 TSYNC 5 TLCLK TLINK Notes: 1. TSYNC is in the output mode (TCR2.2 = 1). 2. TSYNC is in ...
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Figure 24-12 TRANSMIT SIDE TIMING, ELASTIC STORE ENABLED t R TSYSCLK TSER t D3 TCHCLK TCHBLK TSSYNC Notes: 1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. 2. TCHCLK and ...
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MECHANICAL DESCRIPTION 137 of 137 ...