DS21552L+ Maxim Integrated Products, DS21552L+ Datasheet - Page 71

IC TXRX T1 1-CHIP 5V 100-LQFP

DS21552L+

Manufacturer Part Number
DS21552L+
Description
IC TXRX T1 1-CHIP 5V 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS21552L+

Function
Single-Chip Transceiver
Interface
E1, HDLC, J1, T1
Number Of Circuits
1
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Includes
DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
Product
Framer
Number Of Transceivers
1
Data Rate
64 Kbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
75 mA (Typ)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Ic Interface Type
Parallel, Serial
Supply Voltage Range
4.75V To 5.25V
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
LQFP
No. Of Pins
100
Filter Terminals
SMD
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
NOTE:
The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read.
TMEND
RHALF
THALF
RNE
RPE
TNF
RPS
HSR.6
HSR.5
HSR.4
HSR.3
HSR.2
HSR.1
HSR.0
Receive Packet End. Set when the HDLC controller detects either the finish of a valid
message (i.e., CRC check complete) or when the controller has experienced a message
fault such as a CRC checking error, or an overrun condition, or an abort has been seen.
The setting of this bit prompts the user to read the RPRM register for details.
Receive Packet Start. Set when the HDLC controller detects an opening byte. The
setting of this bit prompts the user to read the RPRM register for details.
Receive FIFO Half Full. Set when the receive 64–byte FIFO fills beyond the half way
point. The setting of this bit prompts the user to read the RPRM register for details.
Receive FIFO Not Empty. Set when the receive 64–byte FIFO has at least one byte
available for a read. The setting of this bit prompts the user to read the RPRM register
for details.
Transmit FIFO Half Empty. Set when the transmit 64–byte FIFO empties beyond the
half way point. The setting of this bit prompts the user to read the TPRM register for
details.
Transmit FIFO Not Full. Set when the transmit 64–byte FIFO has at least one byte
available. The setting of this bit prompts the user to read the TPRM register for details.
Transmit Message End. Set when the transmit HDLC controller has finished sending a
message. The setting of this bit prompts the user to read the TPRM register for details.
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