DS21552L+ Maxim Integrated Products, DS21552L+ Datasheet - Page 4

• Manufacturer Part Number: DS21552L+
• Description: IC TXRX T1 1-CHIP 5V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21552L+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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LINE INTERFACE FUNCTION .................................................................................................85
16.1 RECEIVE CLOCK AND DATA RECOVERY ....................................................................85
16.2 TRANSMIT WAVE SHAPING AND LINE DRIVING.......................................................86
16.3 JITTER ATTNUATOR..........................................................................................................86
16.4 PROTECTED INTERFACES................................................................................................92
16.5 RECEIVE MONITOR MODE...............................................................................................95
PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION ............96
TRANSMIT TRANSPARENCY ..................................................................................................99
JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .......................99
19.1 DESCRIPTION ......................................................................................................................99
19.2 TAP CONTROLLER STATE MACHINE ..........................................................................101
19.3 INSTRUCTION REGISTER ...............................................................................................103
19.4 TEST REGISTERS ..............................................................................................................105
INTERLEAVED PCM BUS OPERATION ..............................................................................109
20.1 CHANNEL INTERLEAVE .................................................................................................111
20.2 FRAME INTERLEAVE.......................................................................................................111
FUNCTIONAL TIMING DIAGRAMS .....................................................................................111
RECEIVE AND TRANSMIT DATA FLOW DIAGRAMS.....................................................123
OPERATING PARAMETERS...................................................................................................125
AC TIMING PARAMETERS AND DIAGRAMS....................................................................126
24.1 MULTIPLEXED BUS AC CHARACTERISTICS .............................................................126
24.2 NON-MULTIPLEXED BUS AC CHARACTERISTICS ...................................................129
24.3 RECEIVE SIDE AC CHARACTERISTICS .......................................................................132
24.4 TRANSMIT AC CHARACTERISTICS..............................................................................136
MECHANICAL DESCRIPTTION ............................................................................................139
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