DS21552L+ Maxim Integrated Products, DS21552L+ Datasheet - Page 44

• Manufacturer Part Number: DS21552L+
• Description: IC TXRX T1 1-CHIP 5V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21552L+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RIR1: RECEIVE INFORMATION REGISTER 1 (Address=22 Hex)
RIR2: RECEIVE INFORMATION REGISTER 2 (Address=31 Hex)
RIR3: RECEIVE INFORMATION REGISTER 3 (Address=10 Hex)
RLOSC
(MSB)
SYMBOL
SYMBOL
SYMBOL
(MSB)
(MSB)
COFA
RLOSC
LRCLC
COFA
TSLIP
RBLC
RPDV
TPDV
RL1
RESF
RESE
TESE
16ZD
SEFE
B8ZS
TESF
JALT
8ZD
FBE
RL1
RL0
LRCLC
POSITION
POSITION
POSITION
8ZD
RL0
RIR1.7
RIR1.6
RIR1.5
RIR1.4
RIR1.3
RIR1.2
RIR1.1
RIR1.0
RIR2.7
RIR2.6
RIR2.5
RIR2.4
RIR2.3
RIR2.2
RIR2.1
RIR2.0
RIR3.7
RIR3.6
RIR3.5
TESF
16ZD
JALT
NAME AND DESCRIPTION
Change of Frame Alignment. Set when the last resync resulted in a change of frame
or multiframe alignment.
Eight Zero Detect. Set when a string of at least eight consecutive zeros (regardless of
the length of the string) have been received at RPOSI and RNEGI.
Sixteen Zero Detect. Set when a string of at least sixteen consecutive zeros (regardless
of the length of the string) have been received at RPOSI and RNEGI.
Receive Elastic Store Full. Set when the receive elastic store buffer fills and a frame
is deleted.
Receive Elastic Store Empty. Set when the receive elastic store buffer empties and a
frame is repeated.
Severely Errored Framing Event. Set when 2 out of 6 framing bits (Ft or FPS) are
received in error.
B8ZS Code Word Detect. Set when a B8ZS code word is detected at RPOSI and
RNEGI independent of whether the B8ZS mode is selected or not via CCR2.6. Useful
for automatically setting the line coding.
Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing bit is received in error.
NAME AND DESCRIPTION
Receive Loss of Sync Clear. Set when the framer achieves synchronization; will
remain set until read.
Line Interface Receive Carrier Loss Clear. Set when the carrier signal is restored;
will remain set until read. See Table 7-2.
Transmit Elastic Store Full. Set when the transmit elastic store buffer fills and a frame
is deleted.
Transmit Elastic Store Empty. Set when the transmit elastic store buffer empties and a
frame is repeated.
Transmit Elastic Store Slip Occurrence. Set when the transmit elastic store has either
repeated or deleted a frame.
Receive Blue Alarm Clear. Set when the Blue Alarm (AIS) is no longer detected; will
remain set until read. See Table 7-2.
Receive Pulse Density Violation. Set when the receive data stream does not meet the
ANSI T1.403 requirements for pulse density.
Transmit Pulse Density Violation. Set when the transmit data stream does not meet
the ANSI T1.403 requirements for pulse density.
NAME AND DESCRIPTION
Receive Level Bit 1. SeeTable 7-1.
Receive Level Bit 0. See Table 7-1.
Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to within 4
TESE
LORC
RESF
TSLIP
44 of 137
FRCL
RESE
RBLC
SEFE
RPDV
–
B8ZS
–
(LSB)
TPDV
(LSB)
(LSB)
FBE
–