DS3170N+ Maxim Integrated Products, DS3170N+ Datasheet - Page 104

• Manufacturer Part Number: DS3170N+
• Description: IC TXRX DS3/E3 100-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3170N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 120mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

have both been sent ten times, all ones are output. In continuous mode, the code from TFCA[5:0] is inserted into a
codeword, and sent until the mode is changed
10.9.3.3 Receive FEAC Processor
The Receive FEAC Processor accepts an incoming data line and extracts all overhead and performs FEAC code
extraction , and Idle detection.
FEAC code extraction determines the codeword boundary by identifying the codeword sequence and extracts the
FEAC code. A FEAC codeword is a repeating 16-bit pattern (see
pattern (0xxxxxx011111111) that contains each FEAC code (C[6:1]). Each time slot is checked for a codeword
sequence. Once a codeword sequence is found, the FEAC code is checked. If the same FEAC code is received in
three consecutive codewords without errors, the FEAC code detection indication is set, and the FEAC code is
stored in the Receive FIFO with the MSB (C[1]) in RFF[0], and the LSB (C[6]) in RFF[5]. The FEAC code detection
indication is cleared if two consecutively received FEAC codewords differ from the current FEAC codeword, or a
FEAC Idle condition is detected.
Idle detection detects a FEAC Idle condition. A FEAC idle condition is declared if sixteen consecutive ones are
received. The FEAC Idle condition is terminated when the FEAC code detection indication is set.
10.9.3.4 Receive FEAC FIFO
The Receive FIFO block contains memory for four FEAC codes (C{1:6]) and controller circuitry for reading and
writing the memory. The Receive FIFO controller functions include filling the memory, tracking the memory fill level,
maintaining the memory read and write pointers, and detecting memory overflow and underflow conditions. The
Receive FIFO accepts data from the Receive FEAC Processor and stores the data in memory. The data is read
from the receive FIFO via the microprocessor interface. The Receive FIFO also outputs FIFO fill status (empty) via
the microprocessor interface. All operations are code based (six bits). The Receive FIFO is considered empty when
it does not contain any data. The Receive FIFO accepts data from the Receive FEAC Processor until full. If a
FEAC code is received while full, the data is discarded and a FIFO overflow condition is declared. If the Receive
FIFO is read while the FIFO is empty, the read is ignored.
10.10 Line Encoder/Decoder
10.10.1 General Description
The B3ZS/HDB3 Decoder converts a bipolar signal to a unipolar signal in the receive direction. B3ZS/HDB3
Encoder converts a unipolar signal to a bipolar signal in the transmit direction.
In the transmit direction, the Encoder receives a unipolar signal, converts it to a bipolar signal, optionally performs
zero suppression encoding, optionally inserts errors, and outputs the bipolar signals.
In the receive direction, the Decoder receives a bipolar signal, monitors it for alarms and errors, optionally performs
zero suppression decoding, and converts it to a unipolar signal.
If the port line interface is configured for a Unipolar mode, the BPV detector will count pulses on the RLCV pin. See
Figure 10-24
Figure 10-23. FEAC Codeword Format
for the locations of the Line Encoder/ Decorder block in the DS3170 device.
LSB
16
0
C6
C5 C4 C3 C2 C1
Receive/Transmit Order
Cx - FEAC Code
104 of 230
0
1
1
Figure
1
DS3170 DS3/E3 Single-Chip Transceiver
10-23). The codeword sequence is the
1
1
1
1
MSB
1
1