DS3170N+ Maxim Integrated Products, DS3170N+ Datasheet - Page 73
![IC TXRX DS3/E3 100-CSBGA](/photos/6/94/69414/100-csbga_21-0153b_sml.jpg)
DS3170N+
Manufacturer Part Number
DS3170N+
Description
IC TXRX DS3/E3 100-CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3170.pdf
(230 pages)
Specifications of DS3170N+
Function
Single-Chip Transceiver
Interface
DS3, E3
Number Of Circuits
1
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
120mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LBGA
Includes
DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
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DS3170 DS3/E3 Single-Chip Transceiver
10.5.1.2 Line Loopback (LLB)
Line loopback is enabled by setting PORT.CR4.LBM[2:0] = X10. DLB and LLB are enabled at the same time when
LBM[2:0] = 110, and only LLB is enabled when LBM[2:0] = 010.
The clock from the receive LIU or the RLCLK pin will be output to the transmit LIU or TCLKO pin. The POS and
NEG data from the receive LIU or the RPOS and RNEG pin will be sampled with the receive clock to time it to the
LIU or pin interface.
When LLB is enabled, unframed all ones AIS can optionally be automatically enabled on the receive data path.
This AIS signal will be output on the RSER pin in framed modes. When DLB and LLB is enabled, the AIS signal
will not be transmitted. See
Figure
10-9.
10.5.1.3 Payload Loopback (PLB)
Payload loopback is enabled by setting PORT.CR4.LBM[2:0] = 011.
The payload loopback copies the payload data from the receive framer to the transmit framer which then re-frames
the payload before transmission. Payload loopback is operational in all framing modes.
When PLB is enabled, unframed all ones AIS transmission can optionally be automatically enabled on the receive
data path. This AIS signal will be output on the RSER. In all PLB modes, the TSOFI input pin is ignored.
The external transmit output pins TDEN and TSOFO/TDEN can optionally be disabled by forcing a zero when PLB
is enabled. See
Figure
10-9.
10.5.1.4 Diagnostic Loopback (DLB)
Diagnostic loopback is enabled by setting PORT.CR4.LBM[2:0] = 1XX. DLB and LLB are enabled at the same time
when LBM[2:0] = 110, only DLB is enabled when LBM[2:0] = 10X or 111.
The Diagnostic loopback sends the transmit data, before line encoding, back to the receive side.
Transmit AIS can still be enabled using PORT.CR1.LAIS[2:0] even when DLB is enabled. See
Figure
10-9.
10.5.2 Loss Of Signal Propagation
The Loss Of Signal (LOS) is detected in the line decoder logic. In unipolar (UNI) line interface modes LOS is never
detected. The LOS signal from the line decoder is sent to the DS3/E3 framer and the top level payload AIS logic
except when DLB is activated. When DLB is activated the LOS signal to the framer and AIS logic is never active.
The LOS status in the line decoder status register is valid in all frame and loop back modes, though it is always off
in the line interface is in the UNI mode.
10.5.3 AIS Logic
There is AIS logic in both the framers and at the top level logic of the port. The framer AIS is enabled by setting the
TAIS bit in the appropriate framer transmit control register (T3, E3-G.751, E3-G.832, or Clear Channel). The top
level AIS is enabled by setting the PORT.CR1.LAIS[2:0] bits (see
Table
10-18). The AIS signal is an unframed all
ones pattern or a DS3 framed 101010… pattern depending on the FM[2:0] mode bits. The DS3 Framed Alarm
Indication Signal (AIS) is a DS3 signal with valid F-bits, M-bits, and P-bits (P
and P
). The X-bits (X
and X
) are
1
2
1
2
set to one, all C-bits (C
) are set to zero, and the payload bits are set to a 1010 pattern starting with a one
XY
immediately after each overhead bit. The DS3 framed AIS pattern is only available in DS3 modes. The unframed
all ones pattern is available in all framing modes including the DS3 modes. The transmit line interface can send
both unframed all ones AIS and DS3 framed AIS patterns from either the AIS generator in the framer or the AIS
generator at the top level.
The AIS signal generated in the framer can be initiated and terminated without introducing any errors in the signal.
When the unframed AIS signal is initiated or terminated, there will be no BPV or CV errors introduced, but there will
be framing errors if a framed mode is enabled. When the DS3 framed AIS signal is initiated or terminated, in
addition to no BPV or CV errors, there should be no framing or P-bit (parity) or CP-bit errors introduced.
The AIS signal generated at the top level will not generate BPV errors but may generate P-bit and CP-bit errors
when the signal is initiated and terminated. The framed DS3 AIS signal will not cause the far end receiver to re-
sync when the signal is initiated, but it may cause a re-sync when terminated if the DS3 frame position in the
framer is changed while the DS3 AIS signal is being generated. A sequence of events can be executed which will
enable the initiation and termination of DS3 AIS or unframed all ones at the top level without any errors introduced.
73 of 230
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