DS3170N+ Maxim Integrated Products, DS3170N+ Datasheet - Page 62
![IC TXRX DS3/E3 100-CSBGA](/photos/6/94/69414/100-csbga_21-0153b_sml.jpg)
DS3170N+
Manufacturer Part Number
DS3170N+
Description
IC TXRX DS3/E3 100-CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3170.pdf
(230 pages)
Specifications of DS3170N+
Function
Single-Chip Transceiver
Interface
DS3, E3
Number Of Circuits
1
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
120mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LBGA
Includes
DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
- Current page: 62 of 230
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Table 10-9. Receive Framer Pin Signal Timing Source Select
10.2.4 Clock Structures On Signal IO Pins
The signals on the input pins (TSOFI, TSER) can be used with any of the clock pins for setup/hold timing on clock
input and output pins. There will be a flop at each input whose clock is connected to the signal from the input or
output clock source pins with as little delay as possible from the signal on the clock IO pins. This means using the
input clock signal before the delays of the internal clock tree to clock the input signals, and using the output clock
signals used to drive the output clock pins to clock the input signals.
The signals on the output pins (TPOS/TDAT, TNEG, TSOFO/TDEN, RSER, RSOFO/RDEN) can be with any of the
clock sources for delay timing. There will be a flop at each output whose clock is connected to the signal from the
input or output clock source pins with as little delay as possible from the signal on the clock IO pins. This means
using the input clock signal before the delays of the internal clock tree to clock the input signals, and using the
output clock signals used to drive the output clock pins to clock the input signals.
1
1
1
0
0
0
0
0
0
0
0
0
PLB (011) or DLB (100) or ALB
DLB (100) or LLB & DLB (110)
DLB (100) or LLB & DLB (110)
not LLB, DLB or PLB (00X)
PLB (011) or DLB (100)
not LLB & DLB (110)
not LLB & DLB (110)
not DLB (100) and
not DLB (100) and
DLB&LLB (110)
LLB (010)
LBM[2:0]
(001)
XXX
XXX
XXX
X
X
X
X
X
X
0
1
0
1
0
1
62 of 230
X
X
X
X
X
X
X
X
X
X
0
1
0
1
1
0
0
0
0
0
1
1
1
1
RCLKO, TLCLK, TCLKO
RLCLK
No valid timing to any input clock pin
RCLKO, TLCLK, TCLKO
RCLKO, TLCLK, TCLKO
RCLKO, TCLKO
RCLKO, TLCLK
RCLKO
No valid timing to any input clock pin
TCLKI
RLCLK
No valid timing to any input clock pin
VALID TIMING TO THESE CLOCK PINS
DS3170 DS3/E3 Single-Chip Transceiver
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