PEB 3086 F V1.4 Infineon Technologies, PEB 3086 F V1.4 Datasheet
PEB 3086 F V1.4
Specifications of PEB 3086 F V1.4
PEB3086FV14NP
PEB3086FV14XP
SP000007571
SP000007572
Related parts for PEB 3086 F V1.4
PEB 3086 F V1.4 Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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Data Sheet Revision History: Previous Version: Page Subjects (major changes since last revision) Chapter 1 Comparison ISAC-S/ISAC-SX Chapter S- Transceiver Synchronization New 3.3.7.2 Chapter Test Functions extended 3.3.11 Chapter CDA Handler Description extended 3.7.1.1 Chapter TIC Bus Access Control: Note ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.5.2.2 States (LT- ...
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Table of Contents 3.8.6 Extended Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 ...
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Table of Contents 4.3.1 ACFG1 - Auxiliary Configuration Register 190 4.3.2 ACFG2 - Auxiliary Configuration Register ...
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Table of Contents 4.6.5 MODEB - Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Logic Symbol of the ISAC- ...
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List of Figures Figure 40 State Transition Diagram of Unconditional Transitions (TE, LT- Figure 41 State Transition Diagram (LT- ...
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List of Figures Figure 78 Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 Comparison of the ISAC-SX with the Previous Version ISAC Table 2 ISAC-SX Pin Definitions and Functions . . . . . . . . . . . . . ...
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Overview The ISDN Subscriber Access Controller ISAC-SX integrates a D-channel HDLC controller and a four wire S/T interface used to link voice/data terminals to the ISDN based on the ISAC-S PEB 2086, and provides enhanced features and ...
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Table 1 Comparison of the ISAC-SX with the Previous Version ISAC-S Operating modes Supply voltage Technology Package Transceiver Transformer ratio for the transmitter receiver Test Functions Microcontroller Interface Command structure of the register access (SCI) Crystal Buffered 7.68 MHz output ...
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IOM-2 Interface Monitor channel programming C/I channels Layer 1 state machine Layer 1 state machine in software Support of IDSL (144kBit/s) Provided D-channel HDLC support D-channel FIFO size FW download support HDLC support (B-channel) FIFO size (B-channel) Reset Signals Data ...
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Reset Sources Interrupt Output Signals Pin SCLK Data Sheet ISAC-SX PEB 3086 RES Input Watchdog C/I Code Change EAW Pin Software Reset INT low active (open drain) by default, reprogrammable to high active (push-pull) 1.536 MHz 16 ISAC-SX PEB 3086 ...
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ISAC-SX ISDN Subscriber Access Controller V 1.4 1.1 Features • Full duplex S/T interface transceiver according to ITU-T I.430 • Successor of ISAC-S PEB 2086 in 3.3 V technology • 8-bit parallel microcontroller interface, Motorola and Siemens/Intel ...
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Auxiliary Interface with general purpose I/O pins and LED drivers • Two programmable timers • Watchdog timer • Software Reset • Multiframe Synchronization • Test loops • Sophisticated power management for restricted power mode • Power supply 3.3 V ...
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Logic Symbol The logic symbol gives an overview of the ISAC-SX functions. It must be noted that not all functions are available simultaneously, but depend on the selected mode. Pins which are marked with a “ * “ are ...
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Typical Applications The ISAC-SX is designed for the user area of the ISDN basic access, especially for subscriber terminal equipment and for exchange equipment with S interface. Figure 2 illustrates the general application fields of the ISAC-SX. S TE(1) ...
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Pin Configuration BCL / SCLK DU DD FSC DCL VSS VSS VDD MODE0 MODE1 / EAW ACL AUX7 AUX6 AUX5 AUX4 AUX3 Figure 3 Pin Configuration of the ISAC-SX Data Sheet P-MQFP-64-1 P-TQFP-64 ...
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Table 2 ISAC-SX Pin Definitions and Functions Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD) Host Interface ...
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Table 2 ISAC-SX Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD) 15 AD6 I/O SDR I 16 AD7 I/O SDX R/W I ...
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Table 2 ISAC-SX Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD) 41 ALE INT OD (O) 5 RES I 38 AMODE I IOM-2 Interface 52 FSC ...
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Table 2 ISAC-SX Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD) 49 BCL/ O SCLK 51 DD I/O (OD I/O (OD) 29 SDS1 O 28 SDS2 O Auxiliary Interface ...
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Table 2 ISAC-SX Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD) 63 AUX4 I/O (OD) 62 AUX5 I/O (OD) 61 AUX6 I/O (OD) Data Sheet Function • Auxiliary Port 4 (input/output) ...
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Table 2 ISAC-SX Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD) 60 AUX7 I/O (OD) Miscellaneous 43 SX1 O 44 SX2 O 47 SR1 I 48 SR2 I 35 XTAL1 I ...
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Table 2 ISAC-SX Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD) 58 MODE1 I EAW I 59 ACL O 27 C768 O 6 RSTO n.c. ...
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Table 2 ISAC-SX Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) MQFP-64 TQFP-64 Open Drain (OD 17, – SS 34, 37, 54 – SSA Data Sheet Function Digital ground (0 V) ...
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Description of Functional Blocks 3.1 General Functions and Device Architecture Figure 4 shows the architecture of the ISAC-SX containing the following functions: • S/T-interface transceiver supporting the modes TE, LT-T, LT-S, NT and Intelligent NT • Different host interface ...
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I/O- and Auxiliary Interrupt Interface Lines 8-bit parallel Figure 4 Functional Block Diagram of the ISAC-SX Data Sheet Description of Functional Blocks Peripheral Devices IOM-2 Interface IOM-2 Handler B-channel D-channel MON HDLC HDLC Handler RX/TX RX/TX FIFOs FIFOs Host Interface ...
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Microcontroller Interfaces The ISAC-SX supports a serial or a parallel microcontroller interface. For applications where no controller is connected to the ISAC-SX microcontroller interface programming is done via the IOM-2 MONITOR channel from a master device. In such applications ...
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Serial Control Interface (SCI) The serial control interface (SCI) is compatible to the SPI interface of Motorola or Siemens C510 family of microcontrollers. The SCI consists of 4 lines: SCL, SDX, SDR and CS. Data is transferred via the ...
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Programming Sequences The basic structure of a read/write access to the ISAC-SX registers via the serial control interface is shown in Figure write sequence: header SDR 7 read sequence: header SDR 7 SDX Figure 6 Serial Control Interface Timing ...
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Header 40 : Non-interleaved A-D-A-D Sequences H The non-interleaved A-D-A-D sequence gives direct read/write access to the complete address range and can have any length. In this mode SDX and SDR can be connected together allowing data transmission on one ...
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Header 41 : Non-interleaved A-D-D-D Sequence H This sequence allows in front of the A-D-D-D write access a non-interleaved A-D-A-D read access. This mode is useful for reading status information before writing to the HDLC XFIFO. The termination condition of ...
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Parallel Microcontroller Interface The 8-bit parallel microcontroller interface with address decoding on chip allows easy and fast microcontroller access. The parallel interface of the ISAC-SX provides three types buses which are selected via pin ALE. The ...
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Indirect Address Mode MODE2:AMOD=1 Address Figure 7 Direct/Indirect Register Address Mode Data Sheet Description of Functional Blocks Direct Address Mode MODE2:AMOD=0 Data Address AD0-7 A0-7 8Fh 8Eh Address DATA 01h ADDRESS 00h 38 ISAC-SX PEB 3086 Data ...
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Interrupt Structure Special events in the device are indicated by means of a single interrupt output, which requests the host to read status information from the device or transfer data from/to the device. Since only one interrupt request pin ...
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All seven interrupt bits in the ISTA register point at interrupt sources in the D-channel HDLC Controller (ICD), B-channel HDLC controller (ICB), Monitor- (MOS) and C/I- (CIC) handler, the transceiver (TRAN), the synchronous transfer (ST) and the auxiliary interrupts (AUXI). ...
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Reset Generation Figure 9 shows the organization of the reset generation of the device. . 125µs £ t £ 250µs C/I Code Change (Exchange Awake) 125µs £ t £ 250µs EAW (Subscriber Awake) 125µs £ t £ 250µs Watchdog ...
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Table 6 Reset Source Selection RSS2 RSS1 C/I Code Bit 1 Bit 0 Change • C/I Code Change (Exchange Awake) A change in the downstream C/I channel (C/I0) generates ...
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BCL clock cycles. The address range of the registers which will be reset at each SRES bit is listed in 3.2.5 Timer Modes The ISAC-SX provides two timers which can be used ...
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Timer 1 The host controls the timer 1 by setting bit CMDRD.STI to start the timer and by writing register TIMR1 to stop the timer. After time period T1 an interrupt (AUXI.TIN1) is generated continuously if CNT single ...
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Activation Indication via Pin ACL The activated state of the S-interface is directly indicated via pin ACL (Activation LED). An LED with pre-resistance may directly be connected to this pin and a low level is driven on ACL as ...
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S/T-Interface The layer-1 functions for the S/T interface of the ISAC-SX are: – line transceiver functions for the S/T interface according to the electrical specifications of ITU-T I.430; – conversion of the frame structure between IOM-2 and S/T interface; ...
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ISAC- ISAC-SX TR LT-T 1) The maximum line attenuation tolerated by the ISAC- kHz. TR ISAC-SX TE1 £ £ .... ISAC-SX TE1 Figure 15 Wiring Configurations in User ...
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S/T-Interface Coding Transmission over the S/T-interface is performed at a rate of 192 kbit/s. 144 kbit/s are used for user data (B1+B2+D), 48 kbit/s are used for framing and maintenance information. Line Coding The following figure illustrates the line ...
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Figure 17 Frame Structure at Reference Points S and T (ITU I.430) – F Framing Bit – L. D.C. Balancing Bit – D D-Channel Data Bit – E D-Channel Echo Bit – F Auxiliary Framing Bit A – N – ...
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S/T-Interface Multiframing According to ITU recommendation I.430 a multiframe provides extra layer 1 capacity in the TE-to-NT direction by using an extra channel between the TE and NT (Q-channel). The Q bits are defined to be the bits in ...
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TE Mode After multiframe synchronization has been established, the Q data will be inserted at the upstream (TE ® NT) F bit position in each 5th S/T frame (see A When synchronization is not achieved or lost, each received F ...
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Multiframe Synchronization (M-Bit) The ISAC-SX offers the capability to control the start of the multiframe from external signals, so applications which require synchronization between different S-interfaces are possible. Such an application is the connection of DECT base stations to ...
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Sample Time FSC DCL FSC detected XTAL SX1 / SX2 MBIT Counter reset The sample time of the MBIT input is related to the rising edge of FSC at the beginning frame -- min ...
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(NT -> TE FSC DD ( MBIT (o) Figure 21 Frame Relationship LT-T mode (M-Bit output) Data Sheet ...
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Data Transfer and Delay between IOM-2 and S/T TE mode In the state F7 (Activated the internal layer-1 statemachine is disabled and XINF of register TR_CMD is programmed to ’011’ the B1, B2, D and E bits ...
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-> -> FSC Mapping of B-Channel Timeslots Mapping of a 4-bit group of D-bits on S and IOM depends ...
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-> -> FSC Figure 24 Data Delay between IOM-2 and S/T Interface with 8 IOM Channels (LT-S/NT mode only) E ...
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Transmitter Characteristics The full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter which is realized as a symmetrical current limited voltage source ( mA). The equivalent circuit of the transmitter is shown in max The ...
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Receiver Characteristics The receiver consists of a differential input stage, a peak detector and a set of comparators. Additional noise immunity is achieved by digital oversampling after the comparators. A simplified equivalent circuit of the receiver is shown in ...
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S/T Interface Circuitry For both, receive and transmit direction a 1:1 transformer is used to connect the ISAC- SX transceiver to the 4 wire S/T interface. Typical transformer characteristics can be found in the chapter on electrical characteristics. The ...
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Protection Circuit for Transmitter SX1 SX2 Figure 29 External Circuitry for Transmitter Figure 29 illustrates the secondary protection circuit recommended for the transmitter. The external resistors (5 ... are required in order to adjust the output voltage ...
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Protection Circuit for Receiver Figure 30 illustrates the external circuitry used in combination with a symmetrical receiver. Protection of symmetrical receivers is rather simple. Note capacitors are optional for noise reduction Figure 30 External Circuitry for ...
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SR2 SR1 Note: Capacitors ( pF) are optional for noise reduction. Figure 31 External Circuitry for Symmetrical Receivers Note: Lower or higher values than may be used as well, however for values above 34 k ...
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Transceiver Enable/Disable The layer-1 part of the ISAC-SX can be enabled/disabled by configuration (see Figure 32) with the two bits TR_CONF0.DIS_TR and TR_CONF2.DIS_TX. By default all layer-1 functions with the exception of the transmitter buffer is enabled (DIS_TR = ...
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Depending on the DIS_TX bit in the TR_CONF2 register the internal local loop can be transparent or non transparent to the S/T line. – The external local loop (external Loop A) is activated in the same way as the internal ...
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Clock Generation Figure 34 shows the clock system of the ISAC-SX. The oscillator is used to generate a 7.68 MHz clock signal (f XTAL (8 kHz), DCL (1536 kHz) and BCL (768 kHz) synchronous to the received S/T frames. ...
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Data Sheet Description of Functional Blocks 67 ISAC-SX PEB 3086 2003-01-30 ...
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Note: The IOM-2 interface is adaptive. This means in LT-S/NT and LT-T mode other frequencies for BCL and DCL are possible in the range of 512-4096 kHz (DCL) and 256-2048 kHz (BCL). For details please refer to the application note ...
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Description of the Receive PLL (DPLL) The receive PLL performs phase tracking between the F/L transition of the receive signal and the recovered clock. Phase adjustment is done by adding or subtracting 0 XTAL period to or ...
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Oscillator Clock Output C768 The ISAC-SX derives its system clocks from an external clock connected to XTAL1 (while XTAL2 is not connected) or from a 7.68 MHz crystal connected across XTAL1 and XTAL2. At pin C768 a buffered 7.68 ...
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Control of Layer-1 The layer-1 activation/ deactivation can be controlled by an internal state machine via the IOM-2 C/I0 channel or by software via the microcontroller interface directly. In the default state the internal layer-1 state machine of the ...
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State machines are the key to understanding the transceiver part of the ISAC-SX. They include all information relevant to the user and enable him to understand and predict the behaviour of the ISAC-SX. The state diagram notation is given in ...
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Leave for the state “F6 synchronized” after INFO 2 has been recognized on the S/T- interface. – Leave for the state “F7 activated” after INFO 4 has been recognized on the S/T- interface. – Leave for any unconditional state ...
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Pending Act. TIM RSY X TIM i4 F5 Unsynchronized i0*TO1 Synchronized Lost Framing ...
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SSP SCP SSP TMA SCP TIM DI Test Mode Figure 40 State Transition Diagram of Unconditional Transitions (TE, LT-T) 3.5.1.2 States (TE, LT-T) F3 Pending Deactivation State after deactivation from the S/T interface by info 0. ...
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Any signal except info detected on the S/T interface. F6 Synchronized The receiver has synchronized and detects info 2. Info 3 is transmitted to synchronize the NT. F7 Activated The receiver has synchronized and detects info 4. ...
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C/I Codes (TE, LT-T) Command Activation Request with priority class 8 Activation Request with priority class 10 Activation Request Loop ARL Deactivation Indication Reset Timing Test mode SSP Test mode SCP Note: In the activated states (AI8, AI10 or ...
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Indication Deactivation Request from F6 Power up Activation request Activation request loop ARL Illegal Code Violation Activation indication loop Activation indication with priority class 8 Activation indication with priority class 10 Deactivation confirmation Data Sheet Abbr. Code Remark DR6 0101 ...
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Infos on S/T (TE, LT-T) Receive Infos on S/T (Downstream) Name info 0 info 2 info 4 info X Transmit Infos on S/T (Upstream) Name info 0 info 1 info 3 Test info 1 Test info 2 Data Sheet ...
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State Machine LT-S Mode 3.5.2.1 State Transition Diagram (LT-S) RST TIM RES DR Reset i0 * RES DC Any State DC RSY ARD i3 G2 Lost Framing S ARD = AR or ARL 2) DI ...
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States (LT-S) G1 deactivated The transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. The clocks are deactivated if MODE1-CFS is set to 1. Activation is ...
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Test mode - SCP Continuous alternating pulses are sent on the S/T-interface. 3.5.2.3 C/I Codes (LT-S) Command Abbr. Deactivation DR Request Reset RES Send Single Pulses SSP Send Continuous SCP Pulses Activation Request AR Activation Request ARL Loop Activation Indication ...
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Indication Abbr. Activation Indication AI Deactivation DI Indication 3.5.2.4 Infos on S/T (LT-S) Receive Infos on S/T (Downstream) I0 INFO 0 detected I0 Level detected (signal different to I0) I3 INFO 3 detected I3 Any INFO other than INFO 3 ...
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State Machine NT Mode 3.5.3.1 State Transition Diagram (NT) RST TIM RES Reset i0 * RES DC Any State AID RSY ARD G2 Lost Framing S RSY DR RSY RSY G3 Lost Framing Figure ...
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States (NT) G1 Deactivated The transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. The clocks are deactivated if the bit MODE1.CFS to 1. Activation is ...
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G4 wait for DR Final state after a deactivation request. The transceiver remains in this state until DC is issued. Unconditional States Test Mode SSP Send Single Pulses Test Mode SCP Send ...
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Command Abbr. Activation Indication AIL Loop Deactivation DC Confirmation Indication Abbr. Timing TIM Receiver not RSY Synchronous Activation Request AR Illegal Code CVR Ciolation Activation Indication AI Deactivation DI Indication Data Sheet Description of Functional Blocks Code Remark 1110 Activation ...
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Command/ Indicate Channel Codes (C/I0) - Overview The table below presents all defined C/I0 codes. A command needs to be applied continuously until the desired action has been initiated. Indications are strictly state orientated. Refer to the state diagrams ...
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Control Procedures 3.6.1 Example of Activation/Deactivation An example of an activation/deactivation of the S/T interface initiated by the terminal with the time relationships mentioned in the previous chapters is shown RSY Figure 43 ...
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Activation initiated by the Terminal INFO 1 has to be transmitted as long as INFO 0 is received. INFO 0 has to be transmitted thereafter as long as no valid INFO (INFO 2 or INFO 4) is received. After ...
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Activation initiated by the Network Termination NT INFO 0 has to be transmitted as long as no valid INFO (INFO 2 or INFO 4) is received. After reception of INFO 2 or INFO 4 transmission of INFO 3 has ...
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IOM-2 Interface The ISAC-SX supports the IOM-2 interface in linecard mode and in terminal mode with single clock and double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD and DU. The rising edge of FSC indicates ...
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IOM-2 Frame Structure (TE Mode) The frame structure on the IOM-2 data ports (DU,DD master device in IOM-2 terminal mode is shown in Figure 46 IOM Ò -2 Frame Structure in Terminal Mode The frame is composed of ...
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IOM-2 Frame Structure (LT-S, LT-T Modes) This mode is used in LT-S and LT-T applications. The frame is a multiplex eight IOM-2 channels (DCL = 4096 kHz, described above. The reset value for assignment to one of ...
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IOM-2 Handler The IOM-2 handler offers a great flexibility for handling the data transfer between the different functional units of the ISAC-SX and voice/data devices connected to the IOM-2 interface. Additionally it provides a microcontroller access to all timeslots ...
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SDS2 SDS1 BCL/SCLK DCL FSC DD DU Figure 48 Architecture of the IOM Handler (Example Configuration) Data Sheet Description of Functional Blocks Data C/I0 B2, B1, D, Data B Data D Data C/I1 Data C/I0 Data Bus TIC Data ...
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Controller Data Access (CDA) With its four controller data access registers (CDA10, CDA11, CDA20, CDA21) the ISAC-SX IOM-2 handler provides a very flexible solution for the host access IOM-2 time slots. The functional unit CDA ...
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TSa 1 0 Enable output input * (EN_O0) (EN_I0) CDAx0 1 0 TSa a,b = 0... the normal mode (SWAP=0) the input of CDAx0 and CDAx1 is enabled via EN_I0 and EN_I1, ...
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Looping Data TSa CDA10 TSa .TSS: .DPS ’0’ .SWAP b) Shifting Data TSa CDA10 .TSS: TSa .DPS ’0’ .SWAP c) Switching Data TSa CDA10 .TSS: TSa .DPS ’0’ .SWAP Figure 50 Examples for Data Access via CDAxy Registers a) ...
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Figure 51 shows the timing of looping TSa from 0...11) via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD 0...11 FSC ...
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Shifting TSa ® TSb within one frame (a,b: 0...11 and b ³ a+2) FSC DU TSa (DD) CDAxy b) Shifting TSa ® TSb in the next frame (a,b: 0...11 and ( <a) FSC DU TSa ...
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Monitoring Data Figure 53 gives an example for monitoring of two IOM-2 time slots each simultaneously. For monitoring on DU and/or DD the channel registers with even numbers (CDA10, CDA20) are assigned to time slots with ...
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Synchronous Transfer While looping, shifting and switching the data can be accessed by the controller between the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). The microcontroller access to the CDAxy registers can be synchronized by means of ...
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Table 10 Examples for Synchronous Transfer Interrupts Enabled Interrupts (Register MSTI) STI STOV ...
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Figure 55 shows some examples based on the timeslot structure. Figure a) shows at which point in time an STI and STOV interrrupt is generated for a specific timeslot. Figure b) is identical to example 3 above, figure c) corresponds ...
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Restrictions Concerning Monitoring and Shifting Data Due to the hardware design, there are some restrictions for the CDA shifting data function and for the CDA monitoring data function. The selection of the CDA registers is restricted if other functional blocks ...
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Example: w CDA1_CR = 00 (inputs and outputs are disabled CDA10 = 5A (example CDA10 = FF (old value of previous programming CDA1_CR = 02 (output of CDA10 is enabled CDA10 = ...
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FSC DD, TS0 TS1 SDS1,2 (Example1) SDS1,2 (Example2) SDS1,2 (Example3) Example 1: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 2: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 3: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 For all examples SDS_CONF.SDS1/2_BCL must be set to “0”. Figure ...
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Strobed IOM-2 Bit Clock The strobed IOM-2 bit clock is active during the programmed window. Outside the programmed window a ’0’ is driven. Two examples are shown in FSC DD, TS0 TS1 SDS1 (Example1) SDS1 (Example2) Setting ...
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IOM-2 Monitor Channel The IOM-2 MONITOR channel (see MONITOR channel between a master mode device and a slave mode device. The MONTIOR channel data can be controlled by the bits in the MONITOR control register (MON_CR). For the transmission ...
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As a slave device the transceiver part of the ISAC-SX is programmed and controlled from a master device on IOM-2 (e.g. ISAR 34 PSB 7115). This is used in applications where no microcontroller is connected directly to the ISAC-SX ...
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P µ MIE = 1 MOX = ADR MXC = 1 MAC = 1 MDA Int. MOX = DATA1 MDA Int. MOX = DATA2 MDA Int. MXC = 0 MAC = 0 Figure 59 MONITOR Channel Protocol (IOM-2) Data Sheet ...
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Before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. This is indicated by a ’0’ in the MONITOR Channel Active MAC status bit. After having written the ...
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A pair of MX and MR in the inactive state for two or more consecutive frames indicates an idle state or an end of transmission. • A start of a transmission is initiated by the transmitter by setting the ...
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MX/MR Treatment in Error Case In the master mode the MX/MR bits are under control of the microcontroller through MXC or MRC, respectively. An abort is indicated by an MAB interrupt or MER interrupt, respectively. In the slave mode the ...
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IOM -2 Frame No (DU (DD) 0 Figure 62 Monitor Channel, Normal End of Transmission 3.7.3.3 MONITOR Channel Programming as a Master Device As a master device the ISAC-SX can program and control other devices ...
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MONITOR Channel Programming as a Slave Device In applications without direct host controller connection the ISAC-SX must operate in the MONITOR slave mode which can be selected by pinstrapping the microcontroller interface pins according transceiver part of the ISAC-SX ...
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Programming Sequence The programming sequence is characterized by a ’1’ being sent in the lower nibble of the received address code. The data structure after this first byte and the principle of a read/ write access to a register is ...
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MONITOR Interrupt Logic Figure 63 shows the MONITOR interrupt structure of the ISAC-SX. The MONITOR Data Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable (MRE) and MR bit Control (MRC). The MONITOR channel End of ...
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In the receive direction, the code from layer-1 is continuously monitored, with an interrupt being generated anytime a change occurs (ISTA.CIC). A new code must be found in two consecutive IOM-2 frames to be considered valid and to trigger a ...
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MASK ICB ST CIC WOV TRAN MOS ICD Interrupt Figure 64 CIC Interrupt Structure 3.7.5 D-Channel Access Control D-channel access control is defined to guarantee all connected TEs and HDLC controllers a fair chance to transmit data in the D-channel. ...
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ICC (7) . TIC-Bus . on IOM-2 . ICC (2) ICC (1) D-channel control Figure 65 Applications of TIC Bus in IOM-2 Bus Configuration The arbitration mechanism is implemented in the last octet in IOM-2 channel 2 of the IOM-2 ...
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DU Figure 66 Structure of Last Octet of Ch2 on DU When the TIC bus is seized by the ISAC-SX, the bus is identified to other devices as occupied via the DU Ch2 Bus Accessed-bit state ’0’ until the access ...
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MON0 Figure 67 Structure of Last Octet of Ch2 on DD The Stop/Go bit is available to other layer-2 devices connected to the IOM-2 interface to determine if they can access the S/T bus D channel. The ...
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D-channel control TE 1 D-channel control D-channel control TE 8 Figure 68 D-Channel Access Control on the S-Interface S-Bus D-channel Access Control in the ISAC-SX The above described priority mechanism is fully implemented in the ...
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S-Bus D-Channel Control in LT-T If the TE frame structure on the IOM-2 interface is selected, the same D-channel access procedures as described in For other frame structures used in LT-T mode, D-channel access handled similarly, ...
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Table 14 ISAC-SX Configuration Settings in Intelligent NT Applications Functional Configuration Block Description Layer 1 Select Intelligent NT mode Layer 2 Enable S/G bit evaluation Note: For mode selection in the TR_MODE register the MODE2/1 bits are used to select ...
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NT D-Channel Controller Transmits Upstream In the initial state (’Ready’ state) neither the local D-channel sources nor any of the terminals connected to the S-bus transmit in the D-channel. The ISAC-SX S-transceiver thus receives BAC = “1” (IOM-2 DU ...
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Terminal Transmits D-Channel Data Upstream The initial state is identical to that described in the last paragraph. When one of the connected S-bus terminals needs to transmit in the D-channel, access is established according to the following procedure: • ...
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Activation/Deactivation of IOM-2 Interface The IOM-2 interface can be switched off in the inactive state, reducing power consumption to a minimum. In this deactivated state is FSC = ’1’, DCL and BCL = ’0’ and the data lines are ...
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After the clocks have been enabled this is indicated by the PU code in the C/I channel and, consequently CIC interrupt. The DU line may be released by resetting the Software Power Up bit IOM_CR =’0’ and the ...
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Asynchronous Awake (LT-S, NT, Int. NT mode) The transceiver is in power down mode (deactivated state) and MODE1.CFS=1 (TR_CONF0.LDD is don’t care in this case). Due to any signal on the line the level detect circuit will asynchronously pull the ...
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Auxiliary Interface 3.8.1 Mode Dependent Functions The AUX interface provides various functions, which depend on the operation mode (TE, LT-T, LT- Intelligent NT mode) selected by pins MODE0 and MODE1/EAW (see Table 15). After reset the pins ...
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INT0, INT1 In all modes two pins can be used as programmable I/O with optional interrupt input capability (default after reset, i.e. both interrupts masked). The INT0/1 pins are general input or output pins like AUX0-5 (see description above). In ...
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For DCL = 1.536 MHz one of the IOM-2 channels can be selected, for DCL = 4.096 MHz any of the eight IOM-2 channels can be selected. The channel select pins have direct effect on the timeslot ...
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D- and B-channel (e.g. ISTAx means ISTAD/ISTAB). 3.8.2 Message Transfer Modes The HDLC controllers can be programmed to operate in various modes, ...
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All frames with valid addresses are accepted and the bytes following the address are transferred to the m P via RFIFOx. Additional information is available in RSTAx. Transparent mode 0 (MDS2-0 = ’110’). Characteristics: no address recognition Every received frame ...
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The control of the data transfer between the CPU and the ISAC-SX is handled via interrupts (ISAC-SX ® Host) and commands (Host ® ISAC- SX). There are three different interrupt indications in the ISTAx registers concerned with ...
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The total length of the frame is contained in the RBCHx and RBCLx registers which contain a 12 bit number (RBC11...0), so frames up to 4095 byte length can be counted frame is longer than 4095 bytes, the ...
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RAM EXMx.RFBS=11 so after the first 4 bytes of a new frame have been stored in the fifo an receive pool full interrupt ISTAx.RPF is set. HDLC Receiver µP RAM HDLC Receiver RSTA The HDLC receiver has written further data ...
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Possible Error Conditions during Reception of Frames If parts of a frame get lost because the receive FIFO is full, the Receive Data Overflow (RDO) byte in the RSTAx byte will be set complete frame is lost, i.e. ...
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N In case of RME the last byte in RFIFO contains 1) * the receive status information RSTA Figure 73 Data Reception Procedures Data Sheet Description of Functional Blocks START Receive Y Message End RME ? N Receive Pool Full ...
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Figure 74 gives an example of an interrupt controlled reception sequence, supposed that a long frame (68 byte) followed by two short frames (12 byte each) are received. The FIFO threshold (block size) is set to 32 byte in this ...
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Receive Frame Structure The management of the received HDLC frames as affected by the different operating modes (see Chapter 3.8.2) is shown in MDS2 MDS1 MDS0 MODE Non Auto/ Non Auto ...
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The ISAC-SX indicates to the host that a new data block can be read from the RFIFOx by means of an RPF interrupt (see previous chapter). User data is stored in the RFIFOx and information about the received frame is ...
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Data Transmission 3.8.4.1 Structure and Control of the Transmit FIFO The cyclic transmit FIFO buffers with a length of 64 byte for D-channel and 128 byte for B-channel have FIFO block sizes (thresholds) of • bytes ...
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XRES, but have to be cleared by reading these interutps. Optionally two additional status conditions can be read by the host: – XDOV (Transmit Data Overflow), indicating that the data block ...
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B-channel) the XPR is initiated when a transmit FIFO space of at least 32 bytes is available to accept further data, i.e. there are still a maximum of 32 bytes (D-channel: 64 bytes - 32 bytes) ...
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Command XTF Figure 76 Data Transmission Procedure Data Sheet Description of Functional Blocks START Transmit N Pool Ready XPR ? Y Write one data block to XFIFO End of N Message ? Y Command XTF+XME End 149 ISAC-SX PEB 3086 ...
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The following description gives an example for the transmission byte frame with a selected block size of 32 byte: • The host writes 32 bytes to the XFIFOx, issues an XTF command and waits for an XPR ...
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Transmit Frame Structure The transmission of transparent frames (XTF command) is shown in For transparent frames, the whole frame including address and control field must be written to the XFIFOx. The host configures whether the CRC is generated and ...
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Transmitter The transmitter sends the data out of the FIFO without manipulation. Transmission is always IOM-2 frame aligned and byte aligned, i.e. transmission starts in the first selected channel (B1, B2, D, according to the setting of register DCI_CR or ...
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HDLC Controller Interrupts The cause of an interrupt related to the HDLC controllers is indicated in the ISTA register by the ICD bit for D-channel and ICB for B-channel. These bits point to the different interrupt sources of the ...
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Test Functions The ISAC-SX provides test and diagnostic functions for the S-interface, the D-channel and each of the two B-channels: • Digital loop via TLP (Test Loop, TMD and TMB registers) command bit The TX path of layer 2 ...
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S interface LT-T mode Test loop 3 is activated with the C/I channel command Activate Request Loop (ARL interface is not required since INFO3 is looped back internally ...
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Detailed Register Description The register mapping of the ISAC-SX is shown in FFh 80h 70h 60h 40h 30h 00h Figure 81 Register Mapping of the ISAC-SX The register address range from 00 and the C/I-channel handler. The register set ...
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The address range from 40 timeslot and data port selection (TSDP) and the control registers (CR) for the transceiver data (TR), Monitor data (MON), HDLC/CI data (HCI) and controller access data (CDA), serial data strobe signal (SDS), IOM interface (IOM) ...
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RBCLD RBC7 RBCHD 0 0 TEI1 TEI2 RSTAD VFR RDO TMD 0 0 CIR0 CODR0 CIX0 CODX0 CIR1 CIX1 Transceiver, Auxiliary Interface NAME TR_ DIS_ BUS CONF0 TR TR_ 0 RPLL_ CONF1 ADJ TR_ DIS_ PDS CONF2 ...
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Transceiver, Auxiliary Interface NAME SQXR2 SQX21SQX22SQX23SQX24SQX31 SQX32SQX33 SQX34 SQRR3 SQR41SQR42SQR43SQR44SQR51SQR52SQR53SQR54 SQXR3 SQX41SQX42SQX43SQX44SQX51 SQX52SQX53 SQX54 ISTATR 0 x MASKTR 1 1 TR_ 0 0 MODE ACFG1 OD7 OD6 ACFG2 A7SEL A5SEL FBS A4SEL ACL AOE OE7 OE6 ARX ...
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CDA_ DPS 0 TSDP11 CDA_ DPS 0 TSDP20 CDA_ DPS 0 TSDP21 BCH_ DPS 0 TSDP_ BC1 BCH_ DPS 0 TSDP_ BC2 TR_ DPS 0 TSDP_ BC1 TR_ DPS 0 TSDP_ BC2 CDA1_ CDA2_ ...
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TRC_CR 0 0 (CI_CS=1) BCH_ DPS_ DCI_CR DPS_ EN_ CI1 CI1 (CI_CS=0) DCIC_CR 0 0 (CI_CS=1) MON_CR DPS EN_ MON SDS1_CR ENS_ ENS_ TSS TSS+1 SDS2_CR ENS_ ENS_ TSS TSS+1 IOM_CR SPU DIS_ AW STI STOV STOV ...
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MOCR MRE MRC MSTA 0 0 MCONF 0 0 Interrupt, General Configuration Registers NAME ISTA ICB 0 MASK ICB 1 AUXI 0 0 AUXM 1 1 MODE1 0 0 MODE2 SRES RES_ ...
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CMDRB RMC RRES MODEB MDS2 MDS1 MDS0 EXMB 1 1 RAH1 RAH2 RBCLB RBC7 RBCHB 0 0 RAL1 RAL2 RSTAB VFR RDO TMB 0 0 RFIFOB XFIFOB Data Sheet 0 0 XTF 0 0 RAC 0 RFBS SRA XCRC RCRC ...
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D-channel HDLC Control and C/I Registers 4.1.1 RFIFOD - Receive FIFO D-Channel 7 RFIFOD A read access to any address within the range 00h-1Fh gives access to the “current” FIFO location selected by an internal pointer which is automatically ...
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ISTAD - Interrupt Status Register D-Channel Value after reset ISTAD RME RPF RME ... Receive Message End One complete frame of length less than or equal to the defined block size (EXMD1.RFBS) or the last part ...
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If an XMR interrupt occurs the transmit FIFO is locked until the XMR interrupt is read by the host (interrupt cannot be read if masked in MASKD). XDU ... Transmit Data Underrun The current transmission of a frame is aborted ...
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STARD - Status Register D-Channel Value after reset STARD XDOV XFW XDOV ... Transmit Data Overflow More than bytes (according to selected block size) have been written to the XFIFOD, i.e. data has ...
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RRES ... Receiver Reset HDLC receiver is reset, the RFIFOD is cleared of any data. STI ... Start Timer 1 The ISAC-SX timer 1 is started when STI is set to one. The timer is stopped by writing to the ...
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MDS2-0 ... Mode Select Determines the message transfer mode of the HDLC controller, as follows: MDS2-0 Mode Number of Address Bytes Reserved Reserved Non-Auto 1 mode Non-Auto 2 ...
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RAC ... Receiver Active The D-channel HDLC receiver is activated when this bit is set to ’1’. If set to ’0’ the HDLC data is not evaluated in the receiver. DIM2-0 ... Digital Interface Modes These bits define the characteristics ...
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RFBS … Receive FIFO Block Size RFBS Bit 6 Bit5 Note: A change of RFBS will take effect after a transmitter command (CMDR.RMC, CMDR.RRES,) has been written SRA … Store Receive Address ...
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TIMR1 - Timer 1 Register Value after reset TIMR1 CNT CNT ... Timer Counter CNT together with VALUE determines the time period T after which a AUXI.TIN1 interrupt will be generated: CNT=0...6:T = CNT x 2.048 ...
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SAP2 - SAPI2 Register Value after reset SAP2 SAPI2 ... SAPI2 value Value of the second programmable Service Access Point Identifier (SAPI) according to the ISDN LAPD-protocol. MLA... Mask Low Address 0 …The TEI address of ...
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RBC8-11 ... Receive Byte Count Four most significant bits of the total number of bytes in a received message (see RBCLD register). Note: Normally RBCHD and RBCLD should be read by the microcontroller after an RME-interrupt in order to determine ...
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Terminal Endpoint Identifier according of the ISDN LAPD-protocol. In non-auto-modes with one-byte address field, TEI2 is a response address, according to X.25 LAPD. EA2 ... Address field Extension ...
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SA1-0 ... SAPI Address Identification TA ... TEI Address Identification SA1-0 are significant in non-automode with a two-byte address field, as well as in transparent mode significant in all modes except in transparent modes 0 and 1. ...
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TMD -Test Mode Register D-Channel Value after reset TMD 0 0 For general information please refer to TLP ... Test Loop The TX path of layer-2 is internally connected with the RX path of layer-2. Data ...
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S/G ... Stop/Go Bit Monitoring Indicates the availability of the upstream D-channel on the S/T interface. 1: Stop 0: Go BAS ... Bus Access Status Indicates the state of the TIC-bus: 0: the ISAC-SX itself occupies the D- and C/I-channel ...
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Note: Access is always granted by default to the ISAC-SX with TIC-Bus Address (TBA2-0, STCR register) ’7’, which has the lowest priority in a bus configuration. 4.1.20 CIR1 - Command/Indication Receive 1 Value after reset CIR1 CODR1 ...
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Transceiver Registers 4.2.1 TR_CONF0 - Transceiver Configuration Register 0 Value after reset TR_ DIS_ BUS CONF0 TR DIS_TR ... Disable Transceiver Setting DIS_TR to “1” disables the transceiver. In order to reenable the transceiver again, a ...
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For general information please refer to LDD ... Level Detection Discard 0: Automatic clock generation after detection of any signal on the line in power down state 1: No clock generation after detection of any signal on the line in ...
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DIS_TX ... Disable Line Driver 0: Transmitter is enabled 1: Transmitter is disabled For general information please refer to PDS ... Phase Deviation Select Defines the phase deviation of the S-transmitter. 0: The phase deviation is 2 S-bits minus 7 ...
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TR_STA - Transceiver Status Register Value after reset TR_ RINF STA Important: This register is used only if the Layer 1 state machine of the ISAC-SX is disabled (TR_CONF0.L1SW = 1) and implemented in software! With ...
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TR_CMD - Transceiver Command Register Value after reset TR_ XINF CMD Important: This register is only writable if the Layer 1 state machine of the ISAC-SX is disabled (TR_CONF0.L1SW = 1)! With the ISAC-SX layer 1 ...
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LP_A ... Loop Analog The setting of this bit corresponds to the C/I command ARL. 0: Analog loop is open 1: Analog loop is closed internally or externally according to the EXLP bit in the TR_CONF0 register For general information ...
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SQXR1- S/Q-Channel TX Register 1 Value after reset SQXR1 0 MFEN MFEN ... Multiframe Enable Used to enable or disable the multiframe structure (see 0: S/T multiframe is disabled 1: S/T multiframe is enabled Readback value ...
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SQX21-24, SQX31-34... Transmitted S Bits (NT mode only) Transmitted S bits in frames and 17 (SQX21-24, subchannel 2), and in frames and 18 (SQX31-34, subchannel 3). 4.2.10 SQRR3 - S/Q-Channel Receive Register 3 Value ...
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Reserved Bits set to “1” in this bit position must be ignored. LD ... Level Detection Any receive signal has been detected on the line. This bit is set to “1” (i.e. an interrupt is generated if not ...
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For general information please refer also to DCH_INH ... D-Channel Inhibit Setting this bit to ’1’ has the effect that the S-transceiver blocks the access to the D- channel inverting the E-bits. MODE2-0 ... Transceiver Mode 000: ...
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Auxiliary Interface Registers 4.3.1 ACFG1 - Auxiliary Configuration Register 1 Value after reset ACFG1 OD7 OD6 For general information please refer to OD7-0 ... Output Driver Select for AUX7 - AUX0 0: output is open drain ...
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A5SEL ... AUX5 Function Select 0: pin AUX5 provides normal I/O functionality. 1: pin AUX5 provides an FSC or BCL signal output (FBOUT) which is selected in ACFG2.FBS. Bit AOE.OE5 is don’t care, the output characteristic (push pull or open ...
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Note: An interrupt is only generated if the corresponding mask bit in AUXM is reset. This configuration is only valid if the corresponding output enable bit in AOE is disabled. For general information please refer to 4.3.3 AOE - Auxiliary ...
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Note and LT modes the pins AUX0-2 are not available as I/O pins. 4.3.5 ATX - Auxiliary Interface Transmit Register Value after reset ATX AT7 AT6 AT7-0 ... Auxiliary Transmit A ’0’ or ’1’ in ...
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IOM-2 and MONITOR Handler 4.4.1 CDAxy - Controller Data Access Register xy 7 CDAxy Data registers CDAxy which can be accessed from the controller. Register CDA10 CDA11 CDA20 CDA21 Data Sheet Controller Data Access Register Register Address 40 H ...
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XXX_TSDPxy - Time Slot and Data Port Selection for CHxy 7 XXX_ DPS 0 TSDPxy Register Register Address CDA_TSDP10 44 H CDA_TSDP11 45 H CDA_TSDP20 46 H CDA_TSDP21 47 H BCH_TSDP_BC1 48 H BCH_TSDP_BC2 49 H TR_TSDP_BC1 4C H ...
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DPS ... Data Port Selection 0:The data channel xy of the functional unit XXX is output on DD. The data channel xy of the functional unit XXX is input from DU. 1:The data channel xy of the functional unit XXX ...
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EN_I1, EN_I0 ... Enable Input CDAx0, CDAx1 0: The input of the CDAx0, CDAx1 register is disabled 1: The input of the CDAx0, CDAx1 register is enabled EN_O1, EN_O0 ... Enable Output CDAx0, CDAx1 0: The output of the CDAx0, ...
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Note: Receive data corresponds to downstream direction, and transmit data corresponds to upstream direction. CS2-0 ... Channel Select for Transceiver D-channel This register is used to select one of eight IOM channels to which the transceiver D-channel data is related ...
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DPS_D ... Data Port Selection for D-Channel Timeslot access 0: The B-channel controller data is output on DD. The B-channel controller data is input from DU. 1: The B-channel controller data is output on DU. The B-channel controller data is ...
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EN_CI1 ... Enable CI1 Handler Data 0: CI1 handler data access is disabled 1: CI1 handler data access is enabled Note: The timeslot for the C/I1 handler cannot be programmed but is fixed to IOM channel 1. D_EN_D ... Enable ...