MC54HC86J Fairchild Semiconductor, MC54HC86J Datasheet

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MC54HC86J

Manufacturer Part Number
MC54HC86J
Description
Manufacturer
Fairchild Semiconductor
Datasheet

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© 1999 Fairchild Semiconductor Corporation
MM74C86M
MM74C86N
MM74C86
Quad 2-Input EXCLUSIVE-OR Gate
General Description
The MM74C86 employs complementary MOS (CMOS)
transistors to achieve wide power supply operating range,
low power consumption and high noise margin these gates
provide basic functions used in the implementation of digi-
tal integrated circuit systems. The N- and P-channel
enhancement mode transistors provide a symmetrical cir-
cuit with output swing essentially equal to the supply volt-
age. No DC power other than that caused by leakage
current is consumed during static condition. All inputs are
protected from damage due to static discharge by diode
clamps to V
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Pin Assignments for DIP and SOIC
CC
and GND.
Package Number
Top View
M14A
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
DS005887.prf
Features
Truth Table
H
L
Wide supply voltage range:
Guaranteed noise margin: 1.0V
High noise immunity: 0.45 V
Low power: TTL compatibility:
Fan out of 2 driving 74L
Low power consumption: 10 nW/package (typ.)
The MM74C86 follows the MM74LS86 Pinout
LOW Level
HIGH Level
Package Description
A
H
H
L
L
Inputs
B
H
H
L
L
October 1987
Revised January 1999
CC
3.0V to 15V
(typ.)
www.fairchildsemi.com
Output
H
H
Y
L
L

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MC54HC86J Summary of contents

Page 1

... Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Top View © 1999 Fairchild Semiconductor Corporation Features Wide supply voltage range: Guaranteed noise margin: 1.0V High noise immunity: 0.45 V ...

Page 2

Absolute Maximum Ratings Voltage at any Pin (Note 1) 0. Operating Temperature Range Storage Temperature Range Power Dissipation ( Dual-In-Line Package Small Outline Operating Range ( Electrical Characteristics Min/max limits apply across temperature ...

Page 3

Typical Performance Characteristics Test Circuits and Waveforms Delays Measured with Input FIGURE 2. Switching Time Waveforms Propagation Delay Time vs Load Capacitance FIGURE 1. AC Test Circuit 3 www.fairchildsemi.com ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow www.fairchildsemi.com Package Number M14A 4 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN ...

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