ADM6999 Infineon Technologies AG, ADM6999 Datasheet
ADM6999
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ADM6999 Summary of contents
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... Edition 2005-11-25 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2005. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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... Rev. 1.1, Modify error word. Modify Pin 98 as P8_Enable 2003-04 Rev. 1.2, Modify MII RXER GND pin, Modify MII RXCLK & TXCLK timing requirement, Remove LEDEN pin to NC, Modify ADM6999/X VLAN example error EEPROM Register 0x11h 2003-05 Rev. 1.3, Change RTX version chip 2004-04 Rev ...
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... Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4.1.1 Address Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4.1.2 Address Recognition and Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4.1.3 Address Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.1.4 Back off Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.1.5 Inter-Packet Gap (IPG 3.4.1.6 Illegal Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.1.7 Half Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.1.8 Full Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.1.9 Broadcast Storm Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.2 Auto TP MDIX Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.3 Port Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Data Sheet 4 ADM6999/X Data Sheet Rev. 1.32, 2005-11-25 ...
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... EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.5.1.1 EEPROM Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.6 EEPROM Access Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4 Serial Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.1 Serial Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.1.1 Serial Management Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.2 Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5 TX/FX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.1 TP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.2 FX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Data Sheet 5 ADM6999/X Data Sheet Rev. 1.32, 2005-11-25 ...
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... LED Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 6 The MII Connection with CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 7 Router Old Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 8 The New Architecture by Using ADM6999 Figure 9 The ADM6999/X Serial Chips EEPROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 10 The difference on writing EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 11 Serial Interface Timing Figure 12 Serial Interface Timing Figure 13 TP Interface ...
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... List of Tables Table 1 ADM6999/X-128 PINS GPSI/RMII Table 2 ADM6999/X-128 PINS ( MII Table 3 LED Corresponding Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 4 Registers Address SpaceRegisters Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 5 Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 6 Register Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 7 Registers Clock DomainsRegisters Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 8 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 9 Per Port Rising Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 10 Per Port Falling Threshold ...
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... ADM6999/X also supports priority features by Port-Base, VLAN and IP TOS field checking. It’s easy for users to set different priority mode in individual port, through a small low-cost micro controller to initialize or on-the-fly to configure ...
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... Applications ADM6999/X in 128-pin PQFP: • SOHO 8-port switch • 8-port switch + Router with CPU interface. • 16/24 Dual-speed hub application enabled by “Hubbing-switch©” mode by 100Mbps-backbone bandwidth. Data Sheet 9 ADM6999/X Data Sheet Introduction Rev. 1.32, 2005-11-25 ...
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... TXP0 124 TXN0 125 GNDA 126 RXP0 127 RXN0 128 VCCAD Figure 1 8 TP/FX PORT + 1 GPSI/RMII PORT 128 Pin Diagram Data Sheet ADM6999 8TX/FX+GPSI/RMII 10 ADM6999/X Data Sheet Input and Output Signals 64 GNDIK 63 (GFCEN) TXD0 62 (P7FX)TXD1 61 (TXD[1]) LDSPD7 60 LDSPD6 59 LDSPD5 58 LDSPD4 57 ...
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... TXP0 124 TXN0 125 GNDA 126 RXP0 127 RXN0 128 VCCAD Figure 2 8 TP/FX PORT + 1 MII PORT 128 Pin Diagram Data Sheet ADM6999 8 TP/ MII 11 ADM6999/X Data Sheet Input and Output Signals 64 GNDIK 63 (GFCEN) TXD0 62 P7FX 61 TXD1 60 TXD2 59 TXD3 GNDO ...
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... Pin Description Table 1 ADM6999/X-128 PINS GPSI/RMII) Pin or Ball Name No. Twisted Pair Interface 126 RXP0 2 RXP1 11 RXP2 15 RXP3 24 RXP4 28 RXP5 37 RXP6 41 RXP7 127 RXN0 1 RXN1 12 RXN2 14 RXN3 25 RXN4 27 RXN5 38 RXN6 40 RXN7 123 TXP0 5 TXP1 8 TXP2 18 TXP3 21 TXP4 31 TXP5 34 TXP6 44 TXP7 124 ...
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... Table 1 ADM6999/X-128 PINS GPSI/RMII) Pin or Ball Name No. 68 RMII/GPSISEL 63 TXD TXD0 GFCEN 62 P7FX TXD1 74 RXD RXD0 73 LNKGPSI CRS2 78 COL RXD1 77 CRS CRS1 72 RXCLK 67 TXCLK CRS3 Data Sheet 1)2) (cont’d) Pin Buffer Function Type Type I PD Strapping pin to set 9th port for GPSI or RMII (half- ...
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... Master 01 Slave0 1x Slave1 Master: ADM6999/X will read 93C66/46 EEPROM first Bank (00h ~ 27h). Slave 0: ADM6999/X will read 93C66 EEPROM second Bank (40h ~ 67h). Slave 1: ADM6999/X will read 93C66 EEPROM third Bank (80h ~ a7h). O 8mA LINK/Activity LED[7:0] Active low indicates link okay on cable, but no activity and B signals on idle stage. “ ...
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... Table 1 ADM6999/X-128 PINS GPSI/RMII) Pin or Ball Name No. 108 DUPCOL1 DUPCOL1 PHYAS1 109 DUPCOL0 ANEN 61 LDSPD7 60 LDSPD6 59 LDSPD5 58 LDSPD4 55 LDSPD3 54 LDSPD2 51 LDSPD1 50 LDSPD0 EEPROM/Management Interface 84 EEDO 80 EECS 81 EECK XOVEN Data Sheet 1)2) (cont’d) Pin Buffer Function Type Type I/O 8mA PD Port1 Duplex Collision LED ...
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... Table 1 ADM6999/X-128 PINS GPSI/RMII) Pin or Ball Name No. 79 EEDI LEDMODE Misc. 85 CKO25M 117 Control 120 RTX 118 VREF 112 RC 113 XI 114 XO 49 TEST Chip Configuration, 2 pins 86 CFG0 Power/Ground 3, 10, 16, 23, GNDA 29, 36, 42, 125 6, 7, 19, 20, VCCA2 32, 33, 45, 122 13, 26, 39, ...
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... Table 1 ADM6999/X-128 PINS GPSI/RMII) Pin or Ball Name No. 116 GNDPLL 115 VCCPLL 47, 52, 64, GNDIK 76, 83, 93, 111 48, 53, 65, VCCIK 75, 82, 94, 110 46, 57, 70, GNDO 87, 99, 104 56, 71, 88, VCC3O 105 69 GND 1) Do not swap TP port +- signal. It may cause link fail when link partner does not support Auto Polarity function. ...
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... Table 2 ADM6999/X-128 PINS ( MII) Pin or Ball Name No. Twisted Pair Interface 126 RXP0 2 RXP1 11 RXP2 15 RXP3 24 RXP4 28 RXP5 37 RXP6 41 RXP7 127 RXN0 1 RXN1 12 RXN2 14 RXN3 25 RXN4 27 RXN5 38 RXN6 40 RXN7 123 TXP0 5 TXP1 8 TXP2 18 TXP3 21 TXP4 31 TXP5 34 TXP6 44 TXP7 124 TXN0 ...
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... Table 2 ADM6999/X-128 PINS ( MII) (cont’d) Pin or Ball Name No. 63 TXD[0] GFCEN 59 TXD3 60 TXD2 61 TXD1 62 P7FX 66 TXEN PHYAS0 108 PHYAS1 102 RXD3 101 RXD2 100 RXD1 74 RXD0 73 RXDV 68 GND 78 COL 77 CRS 72 RXCLK Data Sheet Pin Buffer Function Type Type ...
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... Table 2 ADM6999/X-128 PINS ( MII) (cont’d) Pin or Ball Name No. 67 TXCLK 98 P8_Enable 91 DHALFP8 90 LNKFP8 89 SPDTNP8 LED Interface LEDDATA 109 LEDCLK ANEN EEPROM/Management Interface 84 EEDO 80 EECS 81 EECK XOVEN Data Sheet Pin Buffer Function Type Type I MII Port Transmit Clock Input I MII Port Enable ...
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... Table 2 ADM6999/X-128 PINS ( MII) (cont’d) Pin or Ball Name No. 79 EEDI LEDMODE Misc., 8 pins 85 CKO25M 117 Control 120 RTX 118 VREF 112 RC 113 XI 114 XO 49 TEST Switch function 107 BPEN Chip configuration 86 CFG0 Power/Ground 3, 10, 16, 23, GNDA 29, 36, 42, ...
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... Table 2 ADM6999/X-128 PINS ( MII) (cont’d) Pin or Ball Name No. 121 VCCBIAS 116 GNDPLL 115 VCCPLL 47, 52, 64, GNDIK 76, 83, 93, 111 48, 53, 65, VCCIK 75, 82, 94, 110 46, 57, 70, GNDO 87, 99, 104 56, 71, 88, VCC3O 105 69 GND NC Pin 50, 51, 54, NC 55, 58, 92, 97, 103, 106 Data Sheet ...
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... Receiver The 100Base-X receiver consists of functional blocks required to recover and condition the 125Mbits/s receive data stream. The ADM6999/X implements the 100Base-X receiving state machine diagram as given in ANSI/IEEE Standard 802.3u, Clause 24. The 125Mbits/s receive data stream may originate from the on-chip twisted-pair transceiver in a 100Base-TX application ...
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... XORed by the deciphering LFSR and de-scrambled. In order to maintain synchronization, the de-scrambler continuously monitors the validity of the unscrambled data that it generates. To ensure this, a link state monitor and a hold timer are used to constantly monitor the Data Sheet Descriptions10/100M PHY Block Description 24 ADM6999/X Data Sheet Rev. 1.32, 2005-11-25 ...
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... The ADM6999/X performs the link integrity test as outlined in IEEE 100Base-X (Clause 24) link monitor state diagram. The link status is multiplexed with 10Mbits/s link status to form the reportable link status bit in serial management register 1h, and driven to the LNKACT pin ...
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... A bad start of stream delimiter (Bad SSD error condition that occurs in the 100Base-X receiver if carrier is detected (CRS asserted) and a valid /J/K set of code-group (SSD) is not received. If this condition is detected, then the ADM6999/X will assert RXER and present RXD[3:0] = 1110 to the internal MII for the cycles hat correspond to received 5B code-groups until at least two idle code-groups are detected. ...
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... Operation Modes The ADM6999/X 10Base-T module is capable of operating in either half-duplex mode or full-duplex mode. In half- duplex mode, the ADM6999/X functions as an IEEE 802.3 compliant transceiver with fully integrated filtering. The COL signal is asserted during collisions or jabber events, and the CRS signal is asserted during transmit and receive ...
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... Jabber Function The jabber function monitors the ADM6999/X output and disables the transmitter if it attempts to transmit a longer sized packet than legal. If TXEN is high for greater than 24ms, the 10Base-T transmitter will be disabled. Once disabled by the jabber function, the transmitter stays disabled for the entire time that the TXEN signal is asserted. ...
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... Address is stored in the Address Table. The ADM6999/X searches for the Source Address (SA incoming packet in the Address Table and acts as below: If the SA was not found in the Address Table (a new address), the ADM6999/X waits until the end of the packet (non-error packet) and updates the Address Table. If the SA was found in the Address Table, then aging value of each corresponding entry will be reset to 0 ...
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... Full Duplex Flow Control When full duplex port run out of its receive buffer, a PAUSE packet command will be issued by ADM6999/X to notice the packet sender and to pause transmission. This frame based flow control is totally compliant to IEEE 802.3x. ADM6999/X can issue or receive pause packet. ...
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... Switch devices. All these efforts need extra costs and are not a good solution. ADM6999/X provides Auto MDIX function which can adjust TX+- and RX+- at correct pin. Users can use one by one cable between ADM6999/X and other device. This function can be Enabled/Disabled by hardware pin and EEPROM configuration register 0x01h~0x09h bit 15 ...
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... ADM6999/X will check the port’s user defined four bits of VLAN ID first then check VLAN group register. If the destination port is the same VLAN as the receiving port then this packet will forward to destination port without any change. If destination port is not the same VLAN as the receiving port then this packet will be dropped. ...
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... The ADM6999/X provides three different interfaces to drive the status to the LEDs. Each interface supports visibility of per port’s speed, combined transmit and receive activity and duplex collision status. Different interfaces and color modes are applied according to LEDMODE pin and the configuration of the ADM6999/X latched during the power on reset. Refer to Table 1.3 for an illustration. ...
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... ADM6999/X supports MAC Mode MII. MAC mode MII can directly be connected with PHY. If user wants to connect ADM6999/X with CPU, user must reserve signal as below and set chip at 100M Full Duplex. ADM6999/X will drive 25M clock for MII interface. There is no extra logic at 100M Full Duplex connection. ...
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... EEPROM Content EEPROM provides ADM6999/X many options setting such as: • Port Configuration: Speed, Duplex, Flow Control Capability and Tag/Untag • VLAN & TOS Priority Mapping • Broadcast Storming rate and Trunk • Fiber Select, Auto MDIX select • VLAN Mapping • ...
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... ADM6999/X Data Sheet Page Number Rev. 1.32, 2005-11-25 ...
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... SW can read the register, with write mask the register can be cleared SW can read and write this register Register is readable and writable by SW Writing to the register generates a strobe signal for the HW (1 pdi clock cycle) Register is readable and writable by SW. Description 37 ADM6999/X Data Sheet DescriptionsEEPROM Content Rev. 1.32, 2005-11-25 ...
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... Signature Register ADM6999/X will check register 0 value before read all EEPROM content. If this value does not match with 0x4154h then other values in EEPROM will be useless. ADM6999/X will use internal default value. User can not write Signature register when programming ADM6999/X internal register. ...
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... Port Base Priority Number From 1~0 mapping to Q1~Q0. Default 0. Enable Port Based Priority If this bit turns on then ADM6999/X will not check TOS or VLAN as priority reference. ADM6999/X will check port base priority only. ADM6999/X default is bypass mode which checks port base priority only. If user wants to check VLAN tag priority then he must set chip at Tag mode ...
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... Speed Capability 0 , 10M 100M, default B Auto Negotiation Capability Enable 0 , disable enable, default B 802.3X Flow Control Capability 0 , disable enable, default B Table 40 ADM6999/X Data Sheet DescriptionsEEPROM Content 8. Offset Address Page Number Rev. 1.32, 2005-11-25 ...
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... VID 0, 1 Option Register Bit 9: Replaced VID 0, 1. 1/ADM6999/X will replace packet VID by PVID when coming packet’s VID = 0/ADM6999/X will not replace packet’s VID 0 & 1. VID01_OR VID 0, 1 Option Register Field Bits Type Res 15: Res 8 ro ...
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... Disable, default enable Port6 Trunk port B Enable IPG Leveling 1/92 bit. 0/96 bit. When this bit is enable ADM6999/X will transmit packet out at 96 bit or 92 bit to clean buffer. If user disables this function then ADM6999/X will transmit packet at 96 bit Disable, default B ...
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... B Mapped Priority of Tag Value (VLAN default B Mapped Priority of Tag Value (VLAN default B Mapped Priority of Tag Value (VLAN default B Mapped Priority of Tag Value (VLAN default B Weight Ratio 1:1 1:2 1:3 1:4 43 ADM6999/X Data Sheet DescriptionsEEPROM Content Reset Value 5500 H Rev. 1.32, 2005-11-25 ...
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... B Mapped Priority of Tag Value (TOS default B Mapped Priority of Tag Value (TOS default B Mapped Priority of Tag Value (TOS default B Mapped Priority of Tag Value (TOS default B Weight Ratio 1:1 1:2 1:3 1:4 44 ADM6999/X Data Sheet DescriptionsEEPROM Content Reset Value 5500 H Rev. 1.32, 2005-11-25 ...
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... Bit 12: Canonical Format Indicator (CFI) • Bit[11~0]: VLAN ID. The ADM6999/X will use bit[3:0] as VLAN group. • TOS IP Packet ADM6999/X checks byte 12 &13 if this value is 0800h then ADM6999/X knows this is a TOS priority packet. Type 0800 Byte 12~13 IP header define Byte 14 • ...
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... B Reserved 0 , default B Reserved 0 , default B XCRC 0 , enable CRC Check, default disable CRC check B Reserved 0 , default B Broadcast Storming Enable 0 , disable, default enable B Broadcast Storming Threshold See below table default B 46 ADM6999/X Data Sheet DescriptionsEEPROM Content Reset Value 0040 H Rev. 1.32, 2005-11-25 ...
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... Per Port Falling Threshold 00 All 100TX Disable Not All 100TX Disable Table 11 Drop Scheme for each Queue Discard Mode/ 00 Utilization TBD 0% Data Sheet 01 10 10% 20 10% 0. 25% 47 ADM6999/X Data Sheet DescriptionsEEPROM Content 50% Rev. 1.32, 2005-11-25 ...
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... Res 8 ro Res 7 Res 3:0 ro Below is Bit4, 5 VLAN Tag and MAC application example based on Infineon-ADMtek Co Ltd ADM6999/X. Data Sheet Offset 11 H Description Reserved 11111 , default B Back-pressure Enable This is a global pin for all ports disable enable, default ...
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... ISA bus will become bottleneck of whole system. Figure 7 Router Old Architecture Below is new architecture by using ADM6999/X serial chip VLAN function. The advantages of below are: 1. WAN Port can upgrade to 100/10 Full/Half, Auto MDIX. 2. WAN/LAN Port is programmable and put on the same Switch need of extra NIC and saves lot of costs. ...
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... LAN to LAN/CPU Traffic. ADM6999/X LAN traffic to LAN/CPU only. Traffic to another LAN port will be untag packet. Traffic to CPU is Tag packet with VID = 1. CPU can check VID to distinguish LAN traffic or WAN traffic. 2. WAN to CPU Traffic. ADM6999/X WAN traffic to CPU only. Traffic to CPU is Tagged packet with VID = 2. CPU can check VID to distinguish LAN traffic or WAN traffic. ...
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... CPU to WAN Packet. ADM6999/X CPU Packet to WAN port must add VID = 2 in VLAN filed. ADM6999/X check VID to distinguish LAN traffic or WAN traffic. WAN output packet is Untagged. 5. ADM6999/X learning sequence. ADM6999/X will check VLAN mapping setting first then check learning table. User does not worry about LAN/WAN traffic mix up. ...
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... Disable, default Locks first MAC source address B Port0 MAC Lock 0 , Disable, default Locks first MAC source address B Offset 13 H Description VLAN Mapping Table Port assignment bit Offset ADM6999/X Data Sheet DescriptionsEEPROM Content Reset Value H Reset Value H Rev. 1.32, 2005-11-25 ...
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... All VLAN groups will cover Port8 at 32 group mode. This feature is good for multiple ADM6999/X systems. Data Sheet Description Port 7, Odd VLAN Mapping Table Port 6, Even VLAN Mapping Table Port 5, Odd VLAN Mapping Table Port 4, Even VLAN Mapping Table ...
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... Bits Type Port_3 15:8 rw Port_2 7:0 rw Data Sheet Offset 23 H Description Port1 Buffer threshold control Port0 Buffer threshold control Offset 24 H Description Port3 Buffer threshold control Port2 Buffer threshold control 54 ADM6999/X Data Sheet DescriptionsEEPROM Content Reset Value 0000 H Reset Value 0000 H Rev. 1.32, 2005-11-25 ...
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... Port_7 15:8 rw Port_6 7:0 rw ADM6999/X supports buffer management scheme with dynamic thresholds to ensure the fair share of memory among different port queues. If users need each port to have a fixed threshold, they can configure the Bit14 in the Dynamic threshold management: Bit[7]: The add bit. Bit[6:0]: The offset bits. ...
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... Type Res 15 ro Res 14 ro TBTC 13:8 rw PBTC 7:0 rw Data Sheet Offset 27 H Description Reserved 0 , default B Reserved 0 , default B Total Buffer Threshold Control Port8 Buffer Threshold Control The configuration is the same as the other ports. 56 ADM6999/X Data Sheet DescriptionsEEPROM Content Reset Value 0000 H Rev. 1.32, 2005-11-25 ...
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... H Description Port1 PVID bit 11~4 These 8 bits combine with register 0x02h Bit[13~10] as full 12 bit VID default H Port0 PVID bit 11~4 These 8 bits combine with register 0x01h Bit[13~10] as full 12 bit VID default H 57 ADM6999/X Data Sheet DescriptionsEEPROM Content Reset Value 0000 H Rev. 1.32, 2005-11-25 ...
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... H Description Port3 PVID bit 11~4 These 8 bits combine with register 0x04h Bit[13~10] as full 12 bit VID default H Port2 PVID bit 11~4 These 8 bits combine with register 0x03h Bit[13~10] as full 12 bit VID default H 58 ADM6999/X Data Sheet DescriptionsEEPROM Content Reset Value 0000 H Rev. 1.32, 2005-11-25 ...
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... H Description Port5 PVID bit 11~4 These 8 bits combine with register 0x06h Bit[13~10] as full 12 bit VID default H Port4 PVID bit 11~4 These 8 bits combine with register 0x05h Bit[13~10] as full 12 bit VID default H 59 ADM6999/X Data Sheet DescriptionsEEPROM Content Reset Value 0000 H Rev. 1.32, 2005-11-25 ...
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... Port7 PVID bit 11~4 These 8 bits combine with register 0x08h Bit[13~10] as full 12 bit VID default H Port6 PVID bit 11~4 These 8 bits combine with register 0x07h Bit[13~10] as full 12 bit VID default H Offset ADM6999/X Data Sheet DescriptionsEEPROM Content Reset Value 0000 H Reset Value D000 H Rev. 1.32, 2005-11-25 ...
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... B Tag Shift for VLAN Grouping VLAN Tagshift register. ADM6999/X will select 4/5 bit from total 12 bit VID as VLAN group reference. Select bit from VID depends on bit 11 setting. For example Bit[10:8] = 001, Bit11 = 0,then ADM6999/X will select packet VID4~VID1 as VLAN group mapping very flexible for user on VLAN grouping ...
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... Field Bits Type Port_8 7:0 rw Data Sheet Description Port8 PVID bit 11~4 These 8 bits combine with register default H 62 ADM6999/X Data Sheet DescriptionsEEPROM Content Bit[13~10] as full 12 bit VID. H Rev. 1.32, 2005-11-25 ...
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... Input Keep at least 30 ms after RC from ADM6999/X will read data from EEPROM. After RC from CPU update EEPROM then ADM6999/X will update configuration registers too. When CPU programming EEPROM & ADM6999/X, ADM6999/X recognizes the EEPROM WRITE instruction only. ...
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... little bit different with the timing on writing EEPROM. See below graph. It must be carefully when CS goes down after writing a command, SK must issue at least one clock. This is a difference between ADM6999/X and EEPROM write timing. If the system is without EEPROM then user must write ADM6999/X internal register by 93C66 timing ...
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... ADM6999/X Data Sheet Page Number Rev. 1.32, 2005-11-25 ...
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... Description SW Register is readable and writable by SW Value written by software is ignored by hardware; that is, software may write any value to this field without affecting hardware behavior (= Target for development.) 66 ADM6999/X Data Sheet Page Number ...
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... SW can read and write this register Register is readable and writable by SW Writing to the register generates a strobe signal for the HW (1 pdi clock cycle) Register is readable and writable by SW. Description Offset ADM6999/X Data Sheet Reset Value 0002 1120 H Rev. 1.32, 2005-11-25 ...
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... Port 6 Flow Control Enable 0 , Flow Control Disable 802.3X on for full duplex or back pressure on for half duplex B Port 6 Duplex Status 0 , Half Duplex Full Duplex B Port 6 Speed Status Mbit 100 Mbit ADM6999/X Data Sheet Reset Value 0000 0000 H Rev. 1.32, 2005-11-25 ...
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... Mbit/s B Port 3 Linkup Status 0 , Link is not established Link is established B Port 2 Flow Control Enable 0 , Flow Control Disable 802.3X on for full duplex or back pressure on for half duplex B Port 2 Duplex Status 0 , Half Duplex Full Duplex B 69 ADM6999/X Data Sheet Rev. 1.32, 2005-11-25 ...
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... 802.3X on for full duplex or back pressure on for half duplex B Port 0 Duplex Status 0 , Half Duplex Full Duplex B Port 0 Speed Status Mbit 100 Mbit/s B Port 0 Linkup Status 0 , Link is not established Link is established B 70 ADM6999/X Data Sheet Rev. 1.32, 2005-11-25 ...
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... Half Duplex Full Duplex B Port 8 Speed Status Two bits indicate the operating speed Mbit 100 Mbit 1000 Mbit/s B Port 8 Linkup Status 0 , Link is not established Link is established B 71 ADM6999/X Data Sheet Reset Value 0000 0000 H Rev. 1.32, 2005-11-25 ...
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... Port 3 Cable Broken Port 3 Cable Broken Length Port 2 Cable Broken Port 2 Cable Broken Length Port 1 Cable Broken Port 1 Cable Broken Length Port 0 Cable Broken Port 0 Cable Broken Length Offset ADM6999/X Data Sheet Reset Value 0000 0000 H Reset Value 0000 0000 H Rev. 1.32, 2005-11-25 ...
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... Port 5 Transmit Packet Byte Count TPBC_6 Port 6 Transmit Packet Byte Count TPBC_7 Port 7 Transmit Packet Byte Count Data Sheet Serial ManagementSerial Management Registers Description Port 0 Receive Packet Count Table 18. 73 ADM6999/X Data Sheet Offset Address Page Number ...
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... Port 7 Error Count EC_8 Port 8 Error Count Data Sheet Serial ManagementSerial Management Registers Offset Address ADM6999/X Data Sheet Page Number Rev. 1.32, 2005-11-25 ...
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... Data Sheet Serial ManagementSerial Management Registers Offset 3A H Description Overflow of Port Receive Packet Byte Count Overflow of Port Receive Packet Count 75 ADM6999/X Data Sheet Reset Value 0000 0000 H Rev. 1.32, 2005-11-25 ...
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... Data Sheet Serial ManagementSerial Management Registers Offset 3B H Description Overflow of Port Transmit Packet Byte Count Overflow of Port Transmit Packet Count 76 ADM6999/X Data Sheet Reset Value 0000 0000 H Rev. 1.32, 2005-11-25 ...
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... Data Sheet Serial ManagementSerial Management Registers Offset 3C H Description Overflow of Port Error Count Overflow of Port Collision Count 77 ADM6999/X Data Sheet Reset Value 0000 0000 H Rev. 1.32, 2005-11-25 ...
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... Register + 1, Register (Register is even number) • Register, Register - 1(Register is Odd number) • Example: Read Register 00h then ADM6999/X will drive 01 • Read Register 03h then ADM6999/X will drive 03 • Idle: EESK must send at least one clock at idle time ADM6999/X issue Reset internal counter command • ...
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... Clear dedicate port’s all counters – 0: Clear dedicate counter • Port_number or counter index: User defines clear port or counter • Idle: EECK must send at least one clock at idle time Data Sheet Serial ManagementSerial Interface Timing 79 ADM6999/X Data Sheet Rev. 1.32, 2005-11-25 ...
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... ADM6999 RXP RXN Figure 13 TP Interface Transformer requirement: • TX/RX rate 1:1 • TX/RX central tap connect together to VCCA2. User can change TX/RX pin for easy layout but do not change polarity. ADM6999/X supports auto polarity on receiving side. 5.2 FX Interface ADM6999 Figure 14 FX Interface Data Sheet 1:1 0.01U R1 49 ...
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... Unit Note / Test Condition Max. 3.465 V – 1.9 V – 1.9 V – 1.9 V – – CC – W – 115 °C – 1) Unit Note / Test Condition Max CMOS CC – V CMOS 0.4 V CMOS – V CMOS V – kΩ Rev. 1.32, 2005-11-25 ADM6999/X Data Sheet ...
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... Symbol Values Min. Typ. T – 5120 ESK T 2550 – ESKL T 2550 – ESKH T 10 – ERDS 82 ADM6999/X AC Characteristics 100ms tCONF Unit Note / Test Condition Max. – ms – – ns – 20us 30us tERDS tERDH Unit Note / Test Condition Max. – ns – ...
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... Typ. T – 400 CK T 160 – CKL T 160 – CKH T 10 – TXS T 10 – TXH 83 ADM6999/X Data Sheet AC Characteristics Unit Note / Test Condition Max. – ns – – 1500ns 2000ns 250 0n tTHX Unit Note / Test Condition Max. – ns – 240 ns – ...
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... CKL T 160 – CKH T 0 – CSVA T 200 – RXOD 50ns 100ns tCK tCK tCKL tCKL tCKH tCKH tTXS tTXH 84 ADM6999/X AC Characteristics 2000ns Unit Note / Test Condition Max. – ns – 240 ns – 240 ns – – – ns – 150ns 200ns 250 ns Rev ...
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... Values Min. Typ. T – – CKL T 16 – CKH T 0 – CSVA T 20 – RXOD 85 ADM6999/X Data Sheet AC Characteristics Unit Note / Test Condition Max. – ns – – – – ns – – ns – 200ns Unit Note / Test Condition Max. – ...
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... CK T – 10 CKL T – 10 CKH T 4 – TXS T 2 – TXH T 4 – RXS T 2 – RXH 86 ADM6999/X Data Sheet AC Characteristics 100ns 100 ns Unit Note / Test Condition Max. – ns – – ns – – ns – – ns – – ns – – – – ...
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... CKH T 10 – TXS T 10 – TXH 250 ns tCK tCK tCKH tCKH tOD 87 AC Characteristics 500ns tCKL tCKL Unit Note / Test Condition Max. – ns – – – – ns – – ns – 500ns tCKL tCKL Rev. 1.32, 2005-11-25 ADM6999/X Data Sheet ...
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... Min. Typ – – CKL T 10 – CKH T 4 – SDS T 2 – SDH 88 ADM6999/X Data Sheet AC Characteristics Unit Note / Test Condition Max. – ns – – – – 75ns 100ns Unit Note / Test Condition Max. – ...
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... Package Outlines Figure 25 128 Pin PQFP Package Data Sheet 17.2 +/- 0.2 mm 14.0 +/- 0.1 mm 12 ADM6999/X Data Sheet Package Outlines Rev. 1.32, 2005-11-25 ...
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... Published by Infineon Technologies AG ...