HYB39S256160DT-7.5 Infineon Technologies AG, HYB39S256160DT-7.5 Datasheet

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HYB39S256160DT-7.5

Manufacturer Part Number
HYB39S256160DT-7.5
Description
Manufacturer
Infineon Technologies AG
Datasheet
256 MBit Synchronous DRAM
The HYB39S256400/800/160DT(L) are four bank Synchronous DRAM’s organized as 4 banks x
16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices
achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to a system clock. The chip is
fabricated with INFINEON’s advanced 0.14 µm 256MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply. All 256Mbit components are available in TSOPII-54 and TFBGA-54
packages.
INFINEON Technologies
tCK3
tAC3
tCK2
tAC2
fCK
High Performance:
Fully Synchronous to Positive Clock Edge
0 to 70 °C operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
1, 2, 4, 8 and full page
Multiple Burst Read with Single Write
Operation
Automatic
Command
166
7.5
5.4
-6
6
5
and
143
5.4
7.5
5.4
-7
7
Controlled
-7.5
133
7.5
5.4
10
6
125
10
-8
8
6
6
Precharge
Units
MHz
ns
ns
ns
ns
1
HYB39S256400/800/160DT(L)/DC(L)
Data Mask for Read / Write control (x4, x8)
Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
8192 refresh cycles / 64 ms (7,8 µs)
Random Column Address every CLK
( 1-N Rule)
Single 3.3V +/- 0.3V Power Supply
LVTTL Interface versions
Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
Chipsize Packages:
54 ball TFBGA (12 mm x 8 mm)
-6 parts for PC166 3-3-3 operation
-7 parts for PC133 2-2-2 operation
-7.5 parts for PC133 3-3-3 operation
-8 parts for PC100 2-2-2 operation
256MBit Synchronous DRAM
2002-04-23

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HYB39S256160DT-7.5 Summary of contents

Page 1

MBit Synchronous DRAM High Performance: • -7.5 -8 Units fCK 166 143 133 125 MHz tCK3 tAC3 5 5.4 5 tCK2 7.5 7 tAC2 5.4 5.4 6 ...

Page 2

... PC133-222-520 HYB 39S256800DT-7.5 PC133-333-520 HYB 39S256800DT-8 PC100-222-620 HYB 39S256160DT-6 PC166-333-520 HYB 39S256160DT-7 PC133-222-520 HYB 39S256160DT-7.5 PC133-333-520 HYB 39S256160DT-8 PC100-222-620 HYB39S256800DTL-x HYB39S256160DTL-x HYB39S256xx0DC(L)-x Pin Description: CLK Clock Input Clock Enable CKE CS Chip Select RAS Row Address Strobe CAS Column Address Strobe WE Write Enable ...

Page 3

Pinouts (TSOP-54 DQ0 DQ0 N. DDQ DDQ DDQ DQ1 N.C. N.C. 4 DQ2 DQ1 DQ0 SSQ SSQ SSQ DQ3 N.C. N.C. 7 DQ4 ...

Page 4

Pinouts (TFBGA-54) Pin Configuration for x16 devices VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS UDQM CLK CKE A12 A11 VSS A5 A4 Pin Configuration for ...

Page 5

Pinout for x4, x8 & x16 organised 256M-DRAMs ...

Page 6

Column Addresses A0 - A9, AP, BA0, BA1 Column Address Column Address Counter Buffer Row Row Decoder Decoder Memory Memory Array Array Bank 0 Bank 1 8192 8192 x 1024 x 1024 x 8 Bit x 8 Bit Input Buffer ...

Page 7

Column Addresses A0 - A8, AP, BA0, BA1 Column Address Column Address Counter Buffer Row Row Decoder Decoder Memory Memory Array Array Bank 0 Bank 1 8192 x 512 8192 x 512 x 16 Bit x 16 Bit Input Buffer ...

Page 8

Signal Pin Description Pin Type Signal Polarity Function CLK Input Pulse Positive The system clock input. All of the SDRAM inputs are Edge sampled on the rising edge of the clock. CKE Input Level Active Activates the CLK signal when ...

Page 9

Pin Type Signal Polarity Function DQM Input Pulse Active The Data Input/Output mask places the DQ buffers in a LDQM High high impedance state when sampled high. In Read mode, UDQM DQM has a latency of two clock cycles and ...

Page 10

Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands. Operation Device CKE ...

Page 11

Mode Register Set Table BA0 A12 A11 A10 A9 BA1 A8 A7 Operation Mode Operation Mode M9 Mode 0 burst read / burst write 1 burst read / single write CAS Latency Latency Reserved ...

Page 12

Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional ...

Page 13

In other words, unlike burst lengths and 8, full page burst continues until it is terminated using another command. Similar to the page mode of conventional DRAMs, burst read ...

Page 14

The chip has an on-chip timer and the Self Refresh mode is available. The mode restores the word lines after RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals including ...

Page 15

Bank Selection by Address Bits A10 BA0 BA1 Burst Termination Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst ...

Page 16

Absolute Maximum Ratings Parameter Input / Output voltage relative Power supply voltage Operating Temperature Storage temperature range Power dissipation per SDRAM component Data out current (short circuit) Permanent device damage may occur if “Absolute Maximum Ratings” are ...

Page 17

Operating Currents 3.3 V ± 0 DDQ Parameter & Test Condition Operating Current RC(min) One bank active, ...

Page 18

AC Characteristics 1) 3.3 V ± 0 DDQ Parameter Symbol Clock and Clock Enable Clock Cycle Time ...

Page 19

Parameter Symbol Row Cycle Time during Auto t RFC Refresh Activate(a) to Activate(b) t RRD Command period CAS(a) to CAS(b) Command t CCD period Refresh Cycle Refresh Period (8192 cycles) t REF Self Refresh Exit Time t SREX Read Cycle ...

Page 20

Notes 1. For proper power-up see the operation section of this data sheet timing tests have for LV-TTL versions the 1.4 V crossover point. The transition time is measured between measurements assume with the ...

Page 21

Package Outlines - TSOP Plastic Package P-TSOPII-54 (400 mil, 0.8 mm lead pitch) Thin Small Outline Package, SMD 15˚ ±5˚ 0.8 15˚ ±5˚ 26x 0.8 = 20.8 3) +0.1 0.35 -0. 2.5 max 1) 22.22 ±0.13 ...

Page 22

Package Outlines- TFBGA TFBGA-54 package ( mm, 54 balls) INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM 22 2002-04-23 ...

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