HYB39S64800AT-8 Infineon Technologies AG, HYB39S64800AT-8 Datasheet
HYB39S64800AT-8
Related parts for HYB39S64800AT-8
HYB39S64800AT-8 Summary of contents
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MBit Synchronous DRAM High Performance: • -8 -8B -10 fCK 125 100 100 max. tCK3 tAC3 tCK2 tAC2 Fully Synchronous to Positive Clock Edge • ...
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Ordering Information Type Ordering Code LVTTL-version: HYB 39S64400AT-8 HYB 39S64400AT-8B HYB 39S64400AT-10 HYB 39S64800AT-8 HYB 39S64800AT-8B HYB 39S64800AT-10 HYB 39S64160AT-8 HYB 39S64160AT-8B HYB 39S64160AT-10 HYB 39S64xxx0ATL-8/-10 Pin Description and Pinouts: CLK Clock Input CKE Clock Enable CS Chip Select RAS ...
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VDD VDD VDD DQ0 DQ0 NC VDDQ VDDQ VDDQ NC DQ1 NC DQ1 DQ0 DQ2 VSSQ VSSQ VSSQ NC DQ3 NC NC DQ4 DQ2 VDDQ VDDQ VDDQ NC DQ5 NC DQ1 DQ3 DQ6 VSSQ VSSQ VSSQ NC DQ7 NC VDD ...
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Column address counter Row decoder Memory array Bank 0 4096 x 1024 x 4 bit Block Diagram for 4 bank SDRAM Semiconductor Group Row Addresses Column Addresses A0 - A9, AP, BA0, BA1 A0 - A11, ...
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Column address counter Row decoder Memory array Bank 0 4096 x 512 x 8 bit Block Diagram for 4 banks SDRAM Semiconductor Group Row Addresses Column Addresses A0 - A8, AP, BA0, BA1 A0 - A11, ...
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Column address counter Row decoder Memory array Bank 0 4096x256 x16 bit Block Diagram for 4 banks x 1M x16 SDRAM Semiconductor Group Row Addresses Column Addresses A0 - A7, AP, BA0, BA1 A0 - A11, BA0, BA1 Row address ...
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Signal Pin Description Pin Type Signal Polarity Positive CLK Input Pulse Edge Active CKE Input Level High Active CS Input Pulse Low RAS, Active Input Pulse CAS, WE Low A0 - A11 Input Level BA0,BA1 Input Level Input DQx Level ...
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Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands. Operation Device Row ...
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Address Input for Mode Set (Mode Register Operation) BA0 A11 A10 A9 BA1 A8 Operation Mode Operation Mode BA1 BA0 M11 M10 CAS Latency M6 ...
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Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional ...
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Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time limits the number of random ...
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The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock ...
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Burst Termination Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, use ...
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Absolute Maximum Ratings Operating temperature range ......................................................................................... Storage temperature range......................................................................................– 150 C Input/output voltage .............................................................................................– 0.3 to Vdd+0.3 V Power supply voltage VDD / VDDQ.......................................................................... – 0 4.6 V Power Dissipation............................................. ...
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Operating Currents ( (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition OPERATING CURRENT trc=trcmin., tck=tckmin. Ouputs open, Burst Length = 4, CL=3 All banks operated in random access, all banks operated in ping-pong ...
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AC Characteristics 1) Vdd A SS Parameter Clock and Clock Enable Clock Cycle Time CAS Latency = 3 CAS Latency = 2 Clock Frequency CAS Latency = 3 CAS Latency ...
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Parameter Refresh Cycle Refresh Period (4096 cycles) Self Refresh Exit Time Read Cycle Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency Write Cycle Data Input to Precharge ...
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Notes for AC Parameters: 1. For proper power-up see the operation section of this data sheet timing tests for LV-TTL versions have V crossover point. The transition time is measured between V with the AC output load circuit ...
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Package Outlines Plastic Package P-TSOPII-54 Thin small outline package, SMD 0.8 +0.05 0.4 -0.1 0 22.38 Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side Semiconductor Group ( 400mil, 0.8mm lead pitch) ...
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Timing Diagrams 1. Bank Activate Command Cycle 2. Burst Read Operation 3. Read Interrupted by a Read 4. Read to Write Interval 4.1 Read to Write Interval 4.2 Minimum Read to Write Interval 4.3 Non-Minimum Read to Write Interval 5. ...
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Timing Diagrams (cont’d) 18. Random Row Read ( Interleaving Banks) with Precharge 18.1 CAS Latency = 2 18.2 CAS Latency = 3 19. Random Row Write ( Interleaving Banks) with Precharge 19.1 CAS Latency = 2 19.2 CAS Latency = ...
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Bank Activate Command Cycle (CAS latency = CLK Bank A ADDRESS Row Addr. t RCD Bank A COMMAND NOP Activate : “H” or “L” 2. Burst Read Operation (Burst Length = 4, CAS latency = 2, ...
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Read Interrupted by a Read (Burst Length = 4, CAS latency = CLK READ A COMMAND READ B CAS latency = 2 t DQ’s CK2, CAS latency = 3 t DQ’s CK3, 4.1 Read to ...
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Minimum Read to Write Interval (Burst Length = 4, CAS latency = CLK DQM COMMAND NOP NOP CAS latency = 2 t DQ’s CK2, : “H” or “L” Non-Minimum Read to Write Interval ...
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Burst Write Operation (Burst Length = 4, CAS latency = CLK NOP WRITE A COMMAND DQ’s DIN A 0 The first data element and the Write are registered on the same clock edge. 6.1 Write ...
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Write Interrupted by a Read (Burst Length = 4, CAS latency = CLK COMMAND NOP WRITE A CAS latency = 2 DIN DQ’s CK2, CAS latency = 3 DIN ...
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Burst Read with Auto-Precharge (Burst Length = 4, CAS latency = CLK READ A NOP COMMAND with AP CAS latency = 2 t DQ’s CK2, CAS latency = 3 t DQ’s CK3, Semiconductor Group T2 ...
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Termination of a Full Page Burst Read Operation (CAS latency = CLK READ A NOP COMMAND CAS latency = 2 t DQ’s CK2, CAS latency = 3 t DQ’s CK3, 8.2 Termination of a Full ...
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AC Parameters for Write Timing CLK CK2 CL t CKE CS t CKS RAS CAS RAx t AS Addr RAx CAx ...
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AC Parameters for Read Timing CLK CK2 CKE CKS CS RAS CAS RAx t AS Addr RAx DQM Hi-Z DQ Activate Command Bank A ...
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Mode Register Set CLK CKE t RSC CS RAS CAS WE BS0,BS1 A10,A11 Address Key A0-A9 Precharge Mode Register Set Command Command Command All Banks T10 T12 T11 T13 ...
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Power on Sequence and Auto Refresh (CBR CLK High level CKE is required CS RAS CAS Addr DQM t RP Hi-Z DQ Precharge 1st Auto Refresh Command Command All Banks ...
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Clock Suspension During Burst Read (Using CKE CLK t CK2 CKE CS RAS CAS RAx Addr RAx CAx t CSL DQM Hi-Z DQ Ax0 Activate Read Command Command Clock Suspend ...
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Clock Suspension During Burst Read (Using CKE CLK t CK3 CKE CS RAS CAS RAx Addr RAx CAx DQM Hi-Z DQ Activate Read Command Command Bank A Bank A T6 ...
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Clock Suspension During Burst Write (Using CKE CLK t CK2 CKE CS RAS CAS RAx Addr RAx CAx DQM Hi-Z DQ DAx0 DAx1 Activate Clock Suspend Command 1 Cycle Bank ...
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Clock Suspension During Burst Write (Using CKE CLK t CK3 CKE CS RAS CAS RAx Addr RAx CAx DQM Hi-Z DQ DAx0 Activate Clock Suspend Command 1 Cycle Bank A ...
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Power Down Mode and Clock Suspend CLK t CK2 t CKS CKE CS RAS CAS RAx Addr RAx DQM Hi-Z DQ ACTIVE STANDBY Activate Command Command Bank A Bank A ...
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Self Refresh (Entry and Exit CLK t CKS CKE CS RAS CAS Addr DQM Hi-Z DQ All Banks Self Refresh Entry must be idle ...
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Auto Refresh (CBR CLK t CK2 CKE CS RAS CAS Addr t RP DQM (Minimum Interval) Hi-Z DQ Precharge Auto Refresh Command Command All Banks T10 ...
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Random Column Read (Page within same Bank CLK t CK2 CKE CS RAS CAS RAw Addr RAw CAw DQM Hi-Z DQ Aw0 Activate Read Command Command Bank A Bank A ...
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Random Column Read (Page within same Bank CLK t CK3 CKE CS RAS CAS RAw Addr RAw CAw DQM Hi-Z DQ Activate Read Command Command Bank A Bank A T7 ...
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Random Column Write (Page within same Bank CLK t CK2 CKE CS RAS CAS RBz Addr RBz CBz DQM Hi-Z DQ DBw0 DBw1 DBw2 DBw3 Activate Write Command Command Bank ...
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Random Column Write (Page within same Bank CLK t CK3 CKE CS RAS CAS RBz Addr RBz CBz DQM Hi-Z DQ DBw0 DBw1 DBw2 Activate Write Command Command Bank B ...
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Random Row Read (Interleaving Banks) with Precharge CLK t CK2 High CKE CS RAS CAS RBx Addr RBx CBx t t AC2 RCD DQM Hi-Z DQ Bx0 Bx1 Activate Read ...
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Random Row Read (Interleaving Banks) with Precharge CLK t CK3 High CKE CS RAS CAS RBx Addr RBx CBx t t AC3 RCD DQM Hi-Z DQ Activate Read Command Command ...
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Random Row Write (Interleaving Banks) with Precharge CLK t CK2 High CKE CS RAS CAS RAx Addr RAx CAX CAy t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 DAx4 ...
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Random Row Write (Interleaving Banks) with Precharge CLK t CK3 High CKE CS RAS CAS RAx Addr RAx CAX t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 Activate Write Command ...
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Full Page Read Cycle CLK t CK2 High CKE CS RAS CAS RAx RBx Addr RAx CAx RBx DQM Hi Ax+1 Ax+2 Activate Read Activate Command Command Command ...
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Full Page Read Cycle CLK t CK3 High CKE CS RAS CAS RAx RBx Addr RAx CAx RBx DQM Hi-Z DQ Activate Read Activate Command Command Command Bank A Bank ...
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Full Page Write Cycle CLK t CK2 High CKE CS RAS CAS RAx RBx Addr RAx CAx RBx DQM Hi-Z DQ DAx DAx+1 DAx+2 DAx+3 DAx-1 Activate Command Activate Write ...
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Full Page Write Cycle CLK t CK3 High CKE CS RAS CAS RAx RBx Addr RAx CAx RBx DQM Hi-Z DQ DAx DAx+1 DAx+2 Activate Command Activate Write Bank B ...
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Precharge Termination of a Burst CLK t CK2 High CKE CS RAS CAS RAx Addr RAx CAx DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 Activate Write Precharge Command Command Command ...
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Change List: Rev. 10.98 Semiconductor Group ICC6 for L-version changed from 400 A to 500 A 20 HYB39S64400/800/160AT(L) 64MBit Synchronous DRAM 10.98 ...