SH100G Infineon Technologies AG, SH100G Datasheet
SH100G
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SH100G Summary of contents
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... GCDR3300A The GCDR3300A is a macro to be used within the SH100G Gate Array-environment. This macro is designed for 2.5 - 3.3 GHz applications. It contains a 1:2 demultiplexer and a phase detector (PD) [1] with bit error detection and VCO (fig. 1). The block named ’UP’ and ’DOWN’ represents a mixer circuit for the UP and DOWN signals of the PD and the FD ...
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Pinname Signal class I1,I2 Analog data I3,I4 CML2 tclk I5,I6 ECL2 test I7 Analog control I8 CML I9, I19 Analog I10 Analog I11, I12 CML2 I13, I14 CML2 I15, I16 CML2 I17, I18 CML2 O1,O2 CML2 down O3,O4 CML2 up ...
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Description Block Diagram In figure 1, the internal structure of the macro is shown. The block ALEX represents the combined phase detector and decision circuit [1]. In this block, the data signal is recovered and the UP and DOWN signals ...
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VCC 844 fig. 3: External Parts of the PLL circuit a) negative VCO Supply from external reference (LM385-2.5). b) negative VCO Supply from external reference(TL431(SO8)). c) Integrator (part of Loop filter) e.g. TS3V912. Remark: The values given ...
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Pinout Table 3 shows the pad numbers for the G1 and G2 master with the two possible placements of the macro. Table 4 shows the placement of the connections from the core side. Pin I10 I19 ...
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... X-state. To simulate the demultiplexer part of the macro, a reset (pin8) has to be done. Data recovery Circuit in the SH100G Environment To build a complete PLL with LOS and demultiplexer, some additional circuits in the periphery and in the core area are needed ...
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I1,I2 I3,I4 I5, I10 I11,I12 I13,I14 I15,I16 I17,I18 GCDR3300A FD fig. 4: Internal PLL circuit Frequency Detector For the frequency window detector (FWD) a reference clock (REF) is needed. This reference clock is divided by n, and ...
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REF 1/X VCO fig. 5: Frequency window detector block diagram EARLY LATE VST OUT VCO Counter fig. 6: Waveform frequency detector Semiconductor Group Application Notes EARLY LATE Compare VST VST out START Counter DOWN 8 SH 100 G 1 ...
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LOS A LOS can be generated with the help of the BER signal, pin the GCDR3300A. This can be done with a counter that is reset after a certain time generated by the reference clock. When this ...
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OK REFCL fig. 8: SHIFT The Flip-flops in SHIFT are positive edge triggered Semiconductor Group Application Notes 100 G LOS & NOLOS Vers.: 1.3 ...
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Optical Power /dBm Semiconductor Group Application Notes -3dB -27 - 100 -6dB -7 -9dB -10 10 -11 10 -25 -24 Vers.: 1.3 ...
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DOWN UP 40% UP References [ Alexander: "Clock Recovery from Random Binary Signals", Electronics Letters 11, pp. 541-542, Oct. 1975. Semiconductor Group Application Notes 40% 20% DOWN DOWN UP UP DOWN DOWN ...