PSB4610FV2.2 Infineon Technologies AG, PSB4610FV2.2 Datasheet
PSB4610FV2.2
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PSB4610FV2.2 Summary of contents
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ICs for Communications PCI Interface for Telephony/Data Applications PITA-2 PSB 4610 Version 2.2 Preliminary Data Sheet 01. ...
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PSB 4610 Revision History: Previous Version: Page Page (in previous (in current Version) Version) 181 For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our ...
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Organization of this Data Sheet • Chapter 1, Features Describes the general features of the PITA-2. • Chapter 2, Typical Applications with the PITA-2 Describes typical applications that can be realized with the PITA-2. • Chapter 3, Construction of the ...
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Important Notes about this Data Sheet ________________________________________ What’s New? The organization of the structure follows the guidelines of Information Mapping ________________________________________ What is Information Mapping This is a research based method for the – analysis – structure – presentation of ...
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Table of Contents 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 5.3.1 Information about the GP I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . .98 5.3.2 Timing of the ...
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Introduction ________________________________________ What is the PITA-2? The PITA cost-effective PCI bridge for industrial and communication applications. It supports dual cards and D3cold power management. ________________________________________ The PITA-2 can be used in • ISDN cards. • PC ...
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The PITA-2 offers the following interfaces: Interfaces General Purpose I/O Interface SPI EEPROM Interface Preliminary Data Sheet to find in see chapter 5.3 on page 97 see chapter 5.4 on page 115 2 PSB 4610 01.00 ...
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Features ________________________________________ Compliant with • (PCI requirements) • Bus Specification Version 2.2 • Power Management Specification Version 1.1 ________________________________________ Highlights • Dual Card support (3.3V and 5V signaling environment) • Extensive Pow er ...
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Compatibility • ALIS V2.1 PSB 4596 • ALIS V3.X PSB 4596 • ISDN IOM-2 Components, e.g.: – IEC-Q family – SBCX, SBCX-X • Components consisting of a parallel multiplexed or non multiplexed Intel/ Infineon Interface, e.g: – IPAC, IPAC-X ...
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Typical Applications with the PITA-2 ________________________________________ Overview Besides all the applications that require only a simple PCI interface there are some applications which the PITA-2 is especially suited for. Simple applications benefit from the easy configuration of the PITA-2, ...
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ISDN-U Interface Application with the 3PAC and IEC-Q TE PSB 2113 3PAC PSB 4610 PTA-2 PCI Bus ________________________________________ Preliminary Data Sheet Typical Applications with the PITA-2 PSB21911 IEC Interface SPI EEPROM 6 PSB 4610 U-In terface 01.00 ...
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Construction of the PITA-2 ________________________________________ Overview The PITA-2 provides a Peripheral Component Interconnect (PCI) bus interface which acts as a bridge between the PCI bus and the different controllers and interfaces: • The Parallel Interface Control supports up to ...
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Description of the single Blocks N ame provides PCI Bus • bit interface C ontrol at speeds MHz • Bus Master DMA capability for data passing through the Serial Interface • Target capability for ...
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Description of the single Blocks (cont’d) N ame provides EEPROM • additional C ontrol information, such as – the Subsystem – the Subsystem – extensive pow- General • GP outputs Purpose • GP inputs I/O • GP interrupt Interface inputs ...
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Communication with the PITA-2 ________________________________________ For communication with the PITA-2 the following blocks are used: C omponents PCI Configuration Space PCI Master/Target Controller Interrupt Control Register - Retry C ounter ________________________________________ Preliminary Data Sheet Communication with the PITA-2 10 ...
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PCI Configuration Space ________________________________________ Overview Overview Information about the PCI Configuration Space Access to the PCI Configuration Space Base Address Register Other Registers of the PCI C onfiguration Space ________________________________________ Preliminary Data Sheet Communication with the PITA-2 11 PSB ...
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Information about the PCI Configuration Space ________________________________________ Description The PCI Configuration Space contains information about • the PCI device • the requested address space in the memory space of the PC I system. The address space includes 64 32-bit ...
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Construction of the PCI Configuration Space 31 BIST Max_Lat Power Management Capabilities Data Preliminary Data Sheet evice ID Status Class Code Header Type Latency Timer Base Address Register 0 (Internal Registers) Base Address Register ...
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Description of Register Types Type ________________________________________ Preliminary Data Sheet Description • read only via PC I • these bits are initialized by pinstrapping during PCI reset or by the optional EEPR OM • read ...
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Access to the PCI Configuration Space ________________________________________ Description The PITA-2 supports single 32 bit data transactions for the access to the PCI Configuration Space. ________________________________________ Special Qualities N ame Subsystem ID Subsystem Vendor ID C ardBus CIS Pointer ________________________________________ ...
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Base Address Register ________________________________________ Base Address Registers ase Address Register Base Address Register 0 Base Address Register 1 Base Address Register ________________________________________ Structure of the Address Space of Base Address Register 1 ...
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Configuration Space Register: 04h Type D efault Value D escription ________________________________________ Configuration Space Register: 10h B it 31:12 Type D efault Value B it 11:00 Type Value D escription ________________________________________ Preliminary Data Sheet Memory_Access_Enable RW 0b ...
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Configuration Space Register: 14h B it 31:12 Type D efault Value B it 11:00 Type Value D escription ________________________________________ Configuration Space Register: 18h B it 31:0 Type Value D escription ________________________________________ Configuration Space Register: 1Ch B it 31:0 Type ...
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Configuration Space Register: 20h B it 31:0 Type Value D escription ________________________________________ Configuration Space Register: 24h B it 31:0 Type Value D escription ________________________________________ Preliminary Data Sheet Base Address Register 4 H 0000 0000h Base Address Register 4 is ...
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Other Registers of the PCI Configuration Space ________________________________________ Configuration Space Register: 28h B it 31:0 Type Value D escription B it 31:28 Type Value D escription B it 27:3 Type Value D escription B it 2:0 Type Value D ...
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Note The CardBus function is not supported in this version of the PITA-2. ________________________________________ Configuration Space Register: 2Ch B it 31:20 Type D efault Value B it 19:16 Type Value D escription B it 15:0 Type Value D escription ...
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PCI Master/Target Controller ________________________________________ Introduction The interface of the PCI bus is represented by the PCI Master/Target C ontroller. This controller is part of the PITA-2. The PCI Master/Target C ontroller supports • several types of transactions, • Base ...
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Supported PCI Commands ________________________________________ PCI Master Controller: PCI Command Memory Read Memory Write ________________________________________ PCI Target Controller: PCI Command Memory Read Memory Read Multiple Memory Read Line Memory Write Memory Write and Invalidate C onfiguration Read C onfiguration Write ...
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Overview Overview Transaction Type Burst Read Transaction Type Burst Write Transaction Type Fast Back to Back ________________________________________ Note The following timing diagrams are meant as an example and show transactions to and from the PCI configuration space. ________________________________________ Preliminary ...
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Transaction Type Burst Read ________________________________________ Description • Asserting IR DY and STOP at the first dataphase leads to the disconnection (Disconnect-B) of the burst read transaction by the PITA-2. • STOP is asserted until FRAME is deasserted. • Deassertion ...
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Configuration Space Register: 04h B it 26:25 Type Value D escription ________________________________________ Preliminary Data Sheet DEVSEL_Timing H 01b ‘01’ = medium timing, i.e. the DEVSEL signal will be asserted from the PCI interface with the second positive PCI clock ...
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Transaction Type Burst Write ________________________________________ Description • Asserting IR DY and STOP at the first dataphase leads to the disconnection (Disconnect-B) of the burst write transaction by the PITA-2. • STOP is asserted until FRAME is deasserted. • Deassertion ...
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Configuration Space Register: 04h B it 26:25 Type Value D escription ________________________________________ Preliminary Data Sheet DEVSEL_Timing H 01b ‘01’ = medium timing, i.e. the DEVSEL signal will be asserted from the PCI interface with the second positive PCI clock ...
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Transaction Type Fast Back to Back ________________________________________ Description With the fast back to back transaction a PCI Master Controller can perform • several write transactions • a read transaction as last transaction without setting the PCI bus to IDLE ...
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Configuration Space Register: 04h Type Value D escription Type Value D escription ________________________________________ Preliminary Data Sheet Fast_Back_To_Back_Capability H 1b The PITA-2 supports fast back-to-back. Fast_Back_To_Back_Enable H 0b The PITA-2 itself generates no fast ...
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Interrupt Control Register - Retry Counter ________________________________________ Description • Part of the PCI Master Target Controller • Functionality: 1. Disconnection of the PCI Master transaction with Retry by the addressed PCI Slave. 2. Decrement of the counter. 3. The ...
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Internal Register:1Ch B it 23:16 Type D efault Value D escription ________________________________________ Preliminary Data Sheet Retry C ount R egister RW 00h Hold the number of retries for a single PCI master transaction before the PITA-2 will assert an ...
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Communication with External Components ________________________________________ Introduction This chapter describes the interfaces for communication with devices on the local bus side (i.e. not the PCI bus side). ________________________________________ Interfaces Interfaces Serial DMA Interface Parallel Interface General Purpose I/O Interface SPI ...
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Serial DMA Interface ________________________________________ Introduction The serial D MA interface is used in different modes to transmit and receive 16 bit/ 32 bit data frames. These data frames have different content and structures: • Data • Data/Voice and Command ...
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Overview Overview D MA Controller IOM-2 Mode 1 IOM-2 Mode 2 IOM-2 Mode 3 IOM-2 Modes - Supplementary Description Single Modem Mode V2.1 Single Modem Mode ALIS V3.X D ual Modem/Modem+Voice Mode Loop Back Mode ________________________________________ Preliminary Data Sheet ...
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DMA Controller ________________________________________ Overview Overview Information about the DMA Controller Internal Registers of the DMA Controller ________________________________________ Preliminary Data Sheet Communication with External Com ponents 36 PSB 4610 Page 37 41 01.00 ...
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Information about the DMA Controller ________________________________________ Description For the control of the DMA Controller, three register are implemented in the internal registers: • The Circular Buffer Start Address is a 4-kbyte aligned PCI address w hich points to a ...
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Function of the DMA Algorithm Phase Function 1 The D MA controller reads the 16th data word from the current address in the circular buffer (Actual Circular Buffer Pointer) to the internal TX FIFO. 2 The D MA controller ...
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DMA_Start bit • The reset of the DMA_Start bit stops the DMA transfer immediately. • The assertion of the DMA_Start bit resets the TX and RX FIFO’s. This means that all FIFO data is lost when the D MA ...
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Example for DMA controlled Data Transfer via Circular Buffer The status of the DMA controller: 16 bit frame access mode (ALIS V2.1 mode/IOM-2 mode 1) when three data frames are already written to the TX line. Circular Buffer 31 ...
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Internal Registers of the DMA Controller ________________________________________ Internal Registers: 00h Type D efault Value D escription Type D efault Value D escription Type D efault Value D escription B it ...
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Internal Registers: 00h (cont’ Type D efault Value D escription Type D efault Value D escription ________________________________________ Preliminary Data Sheet Communication with External Com ponents DMA_Write_Counter_Overflow _Int RC 0b This bit is set if ...
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Internal Registers: 04h 31:9 Type Value D escription Type D efault Value D escription B it 7:6 Type Value D escription Preliminary Data Sheet Communication with External Com ponents DMA Control ...
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Internal Registers: 04h (cont’ 5:0 Type D efault Value D escription ________________________________________ Preliminary Data Sheet Communication with External Com ponents DMA Select RW 000000b Used to define the mode for the next DMA transfer: – Mode 1 (’000001’): ...
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Internal Registers: 08h B it 31:12 Type D efault Value B it 11:0 Type Value D escription ________________________________________ Internal Register: 0Ch B it 31:02 Type Value B it 1:0 Type Value D escription Preliminary Data Sheet Communication with External ...
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Internal Register: 1Ch B it 11:0 Type D efault Value D escription ________________________________________ Preliminary Data Sheet Communication with External Com ponents DMA Write Count Register RW 000h 46 PSB 4610 01.00 ...
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IOM-2 Mode 1 ________________________________________ Transmission and Reception of Data in the Circular Buffer Circular Buffer Memory 16 31 0000h don't care 0004h don't care 0008h don't care don't care don't care don't care don't care don't care don't care ...
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Data in Circular Buffer and on Serial DMA Interface (cont’d) D irection Data in Circular Buffer R eceive Bits to circular buffer: [31:16] = don’t care [15:8] [7:0] ________________________________________ Timing Diagram FSC (i) DCL (i) TXD (o) 8 bit B1 ...
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Internal Register: 20h Type D efault Value D escription Type D efault Value D escription ________________________________________ Preliminary Data Sheet Communication with External Com ponents DCL_Out_En RW 0b Bit 1=’0’: The DCL signal is ...
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IOM-2 Mode 2 ________________________________________ Transmission and Reception of Data in the Circular Buffer Circular Buffer Memory 16 31 0000h don't care 0004h don't care 0008h don't care don't care don't care don't care don't care don't care don't care ...
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Data in Circular Buffer and on Serial DMA Interface (cont’d) D irection Buffer Offset Transmit ... R eceive ... ... ________________________________________ Timing Diagram FSC (i) DCL (i) TXD (o) 8 bit ...
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Internal Registers: 04h B it 5:0 Type D efault Value D escription ________________________________________ Internal Register: 20h Type D efault Value D escription Type D efault Value D escription ________________________________________ Preliminary Data Sheet Communication ...
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IOM-2 Mode 3 ________________________________________ Transmission and Reception of Data in the Circular Buffer Circular Buffer Memory 16 31 0000h don't care 0004h don't care 0008h don't care don't care don't care don't care don't care don't care don't care ...
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Data in Circular Buffer and on Serial DMA Interface (cont’d) Direction Buffer Offset Transmit ... R eceive ... ... ________________________________________ Timing Diagram FSC (i) DCL (i) TXD (o) 8 bit B1 ...
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Internal Registers: 04h B it 5:0 Type D efault Value D escription ________________________________________ Internal Register: 20h Type D efault Value D escription Type D efault Value D escription ________________________________________ Preliminary Data Sheet Communication ...
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IOM-2 Modes - Supplementary Description ________________________________________ Selection of IOM-2 Time Slots The MISC register contains four bits. They are used for masking the time slot on IOM-2. If Bx_MSK (x := [1,4]) is set: • The corresponding value from ...
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Abbreviations for the Timing Diagram Parameter FSC pulse width FSC setup time FSC hold time D CL cycle time D CL HIGH time D CL LOW time IOM output data delay IOM input data setup IOM input data hold ...
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Masking of IOM-2 Time slots (Example for IOM-2 Mode 2) IOM-2 DU line TXD (0) 'FFh' IOM-2 DD line RXD (i) Circular Buffer Memory Data 3 Data 3 Data 2 Data 2 Data 1 Data 1 ________________________________________ Preliminary Data ...
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Internal Register: 1Ch Type D efault Value D escription Type D efault Value D escription Type D efault Value D escription Preliminary Data Sheet Communication with External ...
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Internal Register: 1Ch (cont’ Type D efault Value D escription ________________________________________ Preliminary Data Sheet Communication with External Com ponents IOM_Supl_masking / IC2_masking RW 0b Address:=’0’: Byte D, C/I0, MR generated out of ...
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Single Modem Mode V2.1 ________________________________________ Data in Circular Buffer and on Serial DMA Interface Direction Transmit R eceive ________________________________________ Timing diagrams FSC (i) DCL (o) TXD (o) RXD (i) FSC (i) t DCD DCL ( RXD (i) ...
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Abbreviations for the Timing Diagram Parameter FSC pulse width D CL delay D CL idle time D CL cycle time D CL HIGH time D CL LOW time D CL duty cycle Input data setup Input data hold Output ...
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PITA Configuration for ALIS V2.1 after a System Reset Serial DMA Interface Mode ALIS V2.1 ________________________________________ Note A Pull Down resistor is required on the board to avoid a floating FSC signal in this situation. ________________________________________ Internal Registers: 04h ...
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Internal Register: 20h Type D efault Value D escription Type D efault Value D escription ________________________________________ Preliminary Data Sheet Communication with External Com ponents DCL_Out_En RW 0b Bit 1=’1’: The DCL signal is ...
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Single Modem Mode ALIS V3.X ________________________________________ Overview Overview Information about the Single Modem Mode ALIS V3.X Internal Registers of the Single Modem Mode V3.X ________________________________________ 5.1.9.1 Information about the Single Modem Mode ALIS V3.X ________________________________________ Data in Circular Buffers, ...
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Note The timing characteristics of the serial D MA interface in Single modem mode V3.X mode are identical to the IOM-2 modes with the only difference that the DC L signal is not a double bit clock, but a ...
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Internal Registers of the Single Modem Mode V3.X ________________________________________ Internal Registers: 04h B it 5:0 Type D efault Value D escription ________________________________________ Internal Register: 10h B it 31:0 D escription B it 31:25 Type Value D escription Preliminary Data ...
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Internal Register: 10h (cont’ Type D efault Value D escription B it 23:16 Type D efault Value D escription Preliminary Data Sheet Communication with External Com ponents New_ALIS_Command_1 RW 0b Bit 24=’1’: The host has written a ...
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Internal Register: 10h (cont’ 15:8 Type D efault Value D escription B it 7:0 Type D efault Value D escription ________________________________________ Preliminary Data Sheet Communication with External Com ponents ALIS_Command_1 RW 00h During a DMA transfer in mode ...
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Internal Register: 14h B it 31:0 D efault Value B it 31:25 Type D efault Value D escription Type D efault Value D escription Preliminary Data Sheet Communication with External Com ponents ALIS Command Register 2 ...
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Internal Register: 14h (cont’ 23:16 Type D efault Value D escription B it 15:8 Type D efault Value D escription B it 7:0 Type D efault Value D escription ________________________________________ Preliminary Data Sheet Communication with External Com ponents ...
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Internal Register: 20h Type D efault Value D escription Type D efault Value D escription ________________________________________ Preliminary Data Sheet Communication with External Com ponents DCL_Out_En RW 0b Bit 1=’0’: The DCL signal is ...
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Dual Modem/Modem+Voice Mode ________________________________________ Description • The PITA transmits and receives two 32 bit frames per FSC time slot. • Each 32 bit frames consists of 16 bit data and 16 bit command/data information. • For each of the ...
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Data Organization in the Circular Buffer Circular Buffer Memory 16 31 0000h don't care 0004h don't care 0008h don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't ...
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Timing Diagram for the Dual Modem+Voice Mode FSC (i) DCL (i) TXD (o) 16 bit data RXD (i) 16 bit data ________________________________________ Description of the Timing Diagram • The second 32 bit frame only consists of the 16 bit ...
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Loop Back Mode ________________________________________ Description If Loop_Back_Mode is set to ’1’ transmit data is transferred from the TX FIFO back to the RX FIFO. ________________________________________ Mode Diagram Circular Buffer Memory Data 3 Data 3 Data 2 Data 2 Data ...
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Internal Register: 28h Type D efault Value D escription ________________________________________ Preliminary Data Sheet Communication with External Com ponents Loop_Back_Mode RW 0b • Bit 0=’0’: The serial controller transmits and receives data/ commands through the serial DMA ...
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Parallel Interface ________________________________________ Description The PITA has an 8 bit parallel interface to support three external components. This parallel interface is implemented in multiplexed and non multiplexed mode. It works in Infineon/Intel bus mode. The parallel interface is by ...
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Mapping between PCI Data and Parallel Interface Data D ata on the PCI bus AD31-0 AD[31-8] = Don’t Care AD[7-0] = Parallel Interface Data AD[31-8] = Don’t Care AD[7-0] = Parallel Interface Data ________________________________________ Address Mapping of the 4-kbyte ...
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Modes and Timing of the Parallel Interface Modes and Timing ALE after System Reset ALE after internal Software Reset ALE after setting the Parallel Interface Mode Bit N on Multiplexed Mode (Write Transaction Multiplexed Mode (Read Transaction) ...
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ALE after System Reset ________________________________________ Timing Diagram 1 2 RST PRST ALE WR RD ________________________________________ Description Both ALE and PRST are high during RST and remain high for a maximum of 4 cycles after RST goes deasserted. ________________________________________ Preliminary ...
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ALE after internal Software Reset ________________________________________ Timing Diagram 1 2 PRST ALE WR RD ________________________________________ Description • After the internal Soft Reset is deasserted the same behavior as in „ALE after System R eset“ generated. • The soft reset ...
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ALE after setting the Parallel Interface Mode Bit ________________________________________ Timing Diagram 1 ______ FRAME ____ IRDY _____ TRDY _______ DEVSEL AD31-0 _______ C/BE3-0 _____ STOP ALE ________________________________________ Description • The parallel interface is in non multiplexed mode by default. ...
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Non Multiplexed Mode (Write Transaction) ________________________________________ Timing Diagram FRAME IRDY TRDY DEVSEL AD31-0 ADR C/BE3-0 CMD STOP CS2-0 ALE WR RD PA7-0 XXXX PAD7-0 ________________________________________ Description • After the address phase on the PCI bus (clock3) ...
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Example As an example the value 0A4h shall be written at address 005h of the device connected to CS1. In this example the Base Address Register 1 (BAR1) shall contain the address 20004000h. • CS1 is activated for the ...
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Non Multiplexed Mode (Read Transaction) ________________________________________ Timing Diagram FRAME IRDY TRDY DEVSEL AD31-0 ADR C/BE3-0 CMD STOP CS2-0 ALE WR RD PA7-0 XXXX PAD7-0 ________________________________________ Description • After the address phase on the PCI bus (clock3) ...
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Multiplexed Mode (Write Transaction) ________________________________________ Timing Diagram FRAME IRDY TRDY DEVSEL AD31-0 ADR DATA1 C/BE3-0 CMD XXX0 STOP CS2-0 ALE WR RD PAD7-0 ________________________________________ Description • After the address phase on the PCI bus (clock 3) ...
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Multiplexed Mode (Read Transaction) ________________________________________ Timing Diagram FRAME IRDY TRDY DEVSEL ADR(00) AD31-0 C/BE3-0 CMD STOP CS2-0 ALE WR RD PAD7-0 ________________________________________ Description • After the address phase on the PCI bus (clock 3) and the ...
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Transaction Disconnect with Target Abort ________________________________________ Timing Diagram 1 2 FRAME IRDY TRDY DEVSEL AD31-0 ADR C/BE3-0 CMD STOP CS2-0 ALE WR RD PAD7-0 ________________________________________ Preliminary Data Sheet Communication with External Com ponents DATA ...
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Description C/BE0 = 1: No transaction is started on selected parallel interface, due to the wrong byte enable. The PC I Master Target Controller disconnects the transaction with target abort. ________________________________________ Configuration Space Register: 04h Type ...
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Configuration Space Register: 04h (cont’ Type D efault Value D escription Type D efault Value D escription Type D efault Value D escription ________________________________________ Preliminary Data Sheet Communication with External Com ...
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Transaction Termination with Retry ________________________________________ Description’ Retry means that the PITA finishes a transaction without a data transfer by asserting the signal STOP , because the parallel interface processes another transaction. The PCI Master Target Controller has to repeat ...
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Explanation of ADR/CMD and ADR2/CMD2 AD R/CMD: The PCI Master Target Controller accepts the write transaction AD R2/CMD2: The second transaction is retried. ________________________________________ Preliminary Data Sheet Communication with External Com ponents 93 PSB 4610 01.00 ...
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Timing of the Parallel Interface ________________________________________ Read Timing AD0-AD7 ________________________________________ Write Timing AD0-AD7 ________________________________________ Multiplexed Address Timing ALE AD0-AD7 ________________________________________ Preliminary Data Sheet Communication with External ...
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Non Multiplexed Address Timing A0-A7 ________________________________________ Application Reset and Interrupt Timing Host write access to the register PRST, SRST INTO (i) INTA (o) ________________________________________ Preliminary Data Sheet Communication with External Com ponents ...
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Abbreviations of the Timing Diagrams Parameter ALE pulse width Address setup time to ALE Address hold time from ALE Address latch setup time to WR Address setup time Address hold time ALE guard time R D pulse ...
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General Purpose I/O Interface ________________________________________ Overview Overview Information about the GP I/O Interface Timing of the GP I/O Interface Internal Registers of the GP I/O Interface Input Mode Output Mode Interrupt Mode U sage of the GP I/O Interface ...
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Information about the GP I/O Interface ________________________________________ Description For additional access to external devices with a slow interface behavior a 4 bit General Purpose I/O interface is implemented in the PITA. ________________________________________ Pinning Pin Pin Name 2 GP0 3 ...
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Control Registers for GPx Pins R egister Interrupt C ontrol Register - ICR GP I/O Interface Control Register ________________________________________ Preliminary Data Sheet Communication with External Com ponents Register Bit Description GPx_INT GP Interrupt Status GPx_INT_En GP Interrupt Enable GPx_OUT_En ...
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Timing of the GP I/O Interface ________________________________________ Timing Diagram Host write access GP0-3 (o) Host read access GP0-3 (i) GP0-3 (i) INTA (o) ________________________________________ Abbreviations of the Timing Diagram Parameter GPx Output Data Delay GPx Input Data Setup GPx ...
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Internal Registers of the GP I/O Interface ________________________________________ Internal Register: 00h Type D efault Value D escription Type D efault Value D escription Type D efault Value D escription Preliminary ...
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Internal Register: 00h (cont’ Type D efault Value D escription ________________________________________ Internal Register: 18h Type D efault Value D escription Type D efault Value D escription Preliminary Data Sheet Communication with ...
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Internal Register: 18h (cont’ Type D efault Value D escription Type D efault Value D escription Type D efault Value D escription Type D efault Value D escription ...
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Internal Register: 18h (cont’ Type D efault Value D escription Type D efault Value D escription Type D escription Type D escription Type D escription ...
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Internal Register: 18h (cont’ Type D escription Type D efault Value D escription Type D efault Value D escription Type D efault Value D escription Preliminary Data Sheet ...
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Internal Register: 18h (cont’ Type D efault Value D escription ________________________________________ Preliminary Data Sheet Communication with External Com ponents GP0_OUT RW 0b The GP0 pin is driven with the value written to this output register if the ...
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Input Mode ________________________________________ Description For using a general purpose I/O pin as input pin, the control register must be configured as follows: GPx_OUT_En = ‘0’ GPx_INT_En = ‘0’ [0, 3]) Description of the internal register 18h on ...
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Abbreviations of the Timing Diagram Parameter GPx Input Data Setup GPx Input Data Hold ________________________________________ Preliminary Data Sheet Communication with External Com ponents Symbol Limit Values m in ISU t 30 IHO 108 PSB 4610 Unit max. ...
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Output Mode ________________________________________ Description For using a general purpose I/O pin as output pin, the control register must be configured as follows: GPx_OUT_En = ‘1’ GPx_INT_En = (x := [0, 3]) Description of the internal register 18h on page ...
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Timing Diagram Host write access GP0-3 (o) ________________________________________ Abbreviation of the Timing Diagram Parameter GPx Output Data Delay ________________________________________ Preliminary Data Sheet Communication with External Com ponents t OD valid state Symbol Limit Values m in 110 ...
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Interrupt Mode ________________________________________ Description For using a general purpose I/O pin as output pin, the control register must be configured as follows: GPx_OUT_En = ‘1’ GPx_INT_En = ‘1’ [0, 3]) Description of the internal register 18h on ...
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Abbreviation of the Timing Diagram Parameter GPx Interrupt Output D elay ________________________________________ Preliminary Data Sheet Communication with External Com ponents Symbol Limit Values m in. t IOD 112 PSB 4610 Unit max 01.00 ...
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Usage of the GP I/O Interface as ALIS V2.1 Control Interface ________________________________________ The serial control interface of the ALIS V2.1 can be realized by software using the General Purpose I/O pins. The GP3 pin is used as CS pin ...
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Timing Diagram for a Write Transaction with two Data Bytes transmitted GP3 ( (i) GP2 (o) / DCLK (i) GP1 (i) / DOUT (o) GP0 (o) / DIN (i) ________________________________________ Timing Diagram for a Read Access with ...
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SPI EEPROM Interface ________________________________________ Overview Overview Information about the SPI EEPROM Interface Timing of the SPI EEPROM Interface Internal Registers for the SPI EEPROM Interface ________________________________________ Preliminary Data Sheet Communication with External Com ponents 115 PSB 4610 Page 116 ...
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Information about the SPI EEPROM Interface ________________________________________ Description Three pins are used to provide an SPI bit EEPROM. These pins also do double-duty as part of the General Purpose Interface. Two other pins are also used to select the ...
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Using the EEPROM for customer specific purposes The contents of the EEPROM can be programmed by writing a command to the EEPROM Control Register and initiating a read/write transaction to the EEPROM. ________________________________________ Note If the automatic reconfiguration of ...
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After finishing the transaction: • The EEPROM control module: – Deasserts the EEPROM_Start bit. – Generates an interrupt in the EEPROM Control Int Register, if the EEPROM_Control_Int_en bit is set to ’1’. • If The EEPROM Command Register is ...
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Timing of the SPI EEPROM Interface ________________________________________ Timing Diagram EPCS (o) t CSS SCK (o) SO (i) SI (o) ________________________________________ Abbreviations of the Timing Diagram Parameter C hip Select Setup Time C hip Select Hold Time C hip Select ...
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Abbreviations of the Timing Diagram (cont’d) Parameter Output Data Hold Time Output Disable Time Write Cycle Time ________________________________________ Note The SCK is a strobed clock signal (i. only active as long as valid data is transferred on SI/SO ...
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Internal Registers for the SPI EEPROM Interface ________________________________________ Internal Register: 00h Type D efault Value D escription Type D efault Value D escription ________________________________________ Internal Register: 24h B it 31:0 D efault Value ...
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Internal Register: 24h (cont’ 23:16 Type D efault Value D escription B it 15:8 Type D efault Value D escription B it 7:0 Type D efault Value D escription ________________________________________ Preliminary Data Sheet Communication with External Com ponents ...
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Power Management ________________________________________ Overview Overview Information about the Power Supply Concept Information about the Power Management States C onfiguration Space Registers of the Power Management Electrical Characteristics C ompatibility Issues ________________________________________ Preliminary Data Sheet Power Managem ent 123 PSB ...
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Information about the Power Supply Concept ________________________________________ Three different Power Supplies The PITA-2 has three different power supplies. It may be helpful for the system design to understand the scope of each of these supplies. • VIO This supply ...
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Summary Information Supply Voltage VIO 3. VDD3 3.3V VAUX 3.3V ________________________________________ Preliminary Data Sheet Comm ent For PCI bus only, affects input threshold, almost no current. Should be present at all times. For PCI and local bus, ...
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Information about the Power Management States ________________________________________ Description The PITA-2 supports the Power Management states D0, D1, D2, D3hot and D3cold. The PITA-2 can assert the PME signal even if the PCI clock (CLK) is not running. Furthermore the ...
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D2 • By default the support of the D2 state is disabled in the PITA-2. • D2 can be enabled by configuration by an EEPROM. • Same state behavior as described for the state D1. ________________________________________ D3 • Same ...
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Considerations about Power Consumption and Reporting ________________________________________ Definitions First of all it is important to distinguish between a PCI component and a PCI device. The PCI component is the circuitry that is interfacing the PCI bus example ...
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Coarse Reporting This mechanism is implemented by the Aux Current field (register 40h only possible to report a single range for the max. current drawn by the PCI device and this range only applied for state D3cold. ...
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Data Selected — Data Reported Data Select ________________________________________ Note The unit for all values is Watts. ________________________________________ The Data Scale field modifies the value of the Data field as follows: Data ...
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Configuration Space Registers of the Power Management ________________________________________ Configuration Register related to Power Management There are basically two types of configuration registers related to power management: • Control Registers • Data Registers The control registers (40h and 44h) define ...
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Configuration Space Register: 34h B it 31:8 Type Value D escription B it 7:0 Type Value D escription ________________________________________ Preliminary Data Sheet Reserved H 000000h Reserved Cap_Ptr H 40h The Capabilities Pointer points to the first Power Management Register ...
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Configuration Space Register: 40h Type D efault Value D escription Type D efault Value D escription Type D efault Value D escription Preliminary Data Sheet Power Management ...
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Configuration Space Register: 40h (cont’ Type D efault Value D escription Type D efault Value D escription Type D efault Value D escription Type D efault Value D ...
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Configuration Space Register: 40h (cont’ 24:22 Type D efault Value D escription Type Value D escription Type Value D escription Preliminary Data Sheet Aux Current E 000b This field can be used ...
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Configuration Space Register: 40h (cont’ Type D efault Value D escription B it 18:16 Type D efault Value D escription B it 15:8 Type Value D escription B it 7:0 Type Value D escription Preliminary Data Sheet ...
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Configuration Space Register: 44h B it 31:24 Type Value D escription B it 23:16 Type Value D escription Type D efault Value D escription B it 14:13 Type Value D escription Preliminary Data Sheet DATA_Register H ...
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Configuration Space Register: 44h (cont’ 12:9 Type D efault Value D escription Type D efault Value D escription B it 7:2 Type Value D escription Preliminary Data Sheet Data_Select RW 0h • Values from 0 ...
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Configuration Space Register: 44h (cont’ 1:0 Type D efault Value D escription ________________________________________ Preliminary Data Sheet Power_State RW 00b Power_State=’00’: D0 state (supported by the PITA-2) Power_State=’01’: D1 state (supported by the PITA-2) Power_State=’10’: D2 state (not supported ...
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Configuration Space Register: 48h B it 31:30 Type Value B it 29:28 Type D efault Value D escription B it 27:20 Type D efault Value D escription B it 19:18 Type D efault Value D escription Preliminary Data Sheet ...
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Configuration Space Register: 48h (cont’ 17:10 Type D efault Value D escription B it 9:8 Type D efault Value D escription B it 7:0 Type D efault Value D escription ________________________________________ Preliminary Data Sheet Data for Data Select ...
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Configuration Space Register: 4Ch B it 31:30 Type Value B it 29:28 Type D efault Value D escription B it 27:20 Type D efault Value D escription B it 19:18 Type D efault Value D escription Preliminary Data Sheet ...
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Configuration Space Register: 4Ch (cont’ 17:10 Type D efault Value D escription B it 9:8 Type D efault Value D escription B it 7:0 Type D efault Value D escription ________________________________________ Preliminary Data Sheet Data for Data Select ...
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Configuration Space Register: 50h B it 31:20 Type Value B it 19:18 Type D efault Value D escription B it 17:10 Type D efault Value D escription B it 9:8 Type D efault Value D escription Preliminary Data Sheet ...
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Configuration Space Register: 50h (cont’ 7:0 Type D efault Value D escription ________________________________________ Preliminary Data Sheet Data for Data Select = 6 E 00h This value is mapped to the Data field of register 44h when Data Select ...
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Electrical Characteristics ________________________________________ Vaux Power Supply in different Power Management Modes State D3hot D3cold ________________________________________ Description of the Table The table above shows the current drawn by the V power management modes. The PITA-2 meets the ...
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Design Hints ________________________________________ D3cold For a design that supports D3cold it is important to check all signals on the local bus side of the PITA-2 that may be affected by a missing Vdd3. As during D3cold Vdd3 w ill ...
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Compatibility Issues ________________________________________ Supported Designs by PITA The PITA-2 supports designs which are compliant to the PCI Local Bus Specification R evision 2.2 and the PCI Bus Power Management Interface Specification Revision 1.1. ________________________________________ Potential Compatibility Problem The only ...
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Reset and Interrupts ________________________________________ 7.1 Reset ________________________________________ Introduction After each power up the PITA-2 must be reset. This reset is necessary to establish a well defined state for all subsequent actions. This chapter informs about: • reset phases • ...
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External Signals All PCI signals are floated as long as the R ST signal is low. Significant input signals (GPIO0-GPIO3, PA0-PA7, PAD0-PAD7 and ELD) must remain stable at least six clock cycles after the rising edge of the RST ...
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Pinstrapping Pinstrapping is used for: • Loading the Subsystem Vendor ID. • Loading the least significant 4 bits of the Subsystem ID to the PCI Configuration Space. Several output pins from the parallel micro controller interface and the general ...
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Interrupts ________________________________________ Introduction The PITA-2 can generate an interrupt on the PCI signal INTA • external, asynchronous event (e.g. an incoming call) • internal, synchronous event (e.g. an EEPROM access finished)) ________________________________________ General Notes The PITA-2 can only assert ...
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External Events For external events either the dedicated INT0 pin or one of the General Purpose IO pins (GP0-GP3) can be used. The following table shows how to program the PITA-2 in order to activate one or more of ...
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Internal Events The following internal events can trigger an interrupt when enabled: • an EEPROM command has finished • the programmed number of writes to the DMA buffer has occurred • FIFO overflow (receive failure) • FIFO underflow (transmit ...
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PCI Retries expired The PCI retries expired event is not a normal event but is not necessarily a fatal event. If the PITA-2 reports this event the following has happened: • The DMA controller has requested a data word ...
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Pinning ________________________________________ PITA-2 Pinout This illustration shows the numbered pins and their respective signals: PRST 76 PAD7 77 PAD6 78 PAD5 79 PAD4 80 PAD3 81 PAD2 82 PAD1 83 PAD0 CS0 87 VAUX ...
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Overview The following table lists the interfaces and their respective pins: Interface PCI bus Parallel Interface Serial Interface GP I/O Interface Special EEPROM Signals Power Management ________________________________________ Description of PIN Types Type O/ ________________________________________ Preliminary Data ...
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This table lists the Pins Characteristics of the PCI Bus Pin No. Signal Name 23, AD(31 24, 34, C /BE(3:0) 43 ...
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This table lists the Pins Characteristics of the PCI Bus (cont’d) Pin No. Signal Name CLKRUN ________________________________________ This table lists the Pins Characteristics of the Parallel Interfaces Pin No. Signal Name 76 66, 67, CS(2:0) 87 ...
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This table lists the Pins Characteristics of the Parallel Interfaces (cont’d) Pin No. Signal Name 74 - 68, 65 PA(7: ________________________________________ Preliminary Data Sheet Pin Count 8 ALE INT0 1 160 ...
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This table list the Pins Characteristics of the Serial Interface Pin No. Signal Name ________________________________________ Preliminary Data Sheet Pin Count SRST 1 FSC 1 DCL 1 RXD 1 TXD 1 161 PSB 4610 Type ...
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This table lists the Pins Characteristics of the General Purpose I/O Interface Pin No. Signal Name ________________________________________ Preliminary Data Sheet Pin Count GP3 1 GP2 1 GP1 1 GP0 1 162 PSB 4610 Type Function ...
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This table lists the Pins Characteristics of the Special EEPROM Signals Pin No. Signal Name 99 100 ________________________________________ Preliminary Data Sheet Pin Count ELD 1 ECS 1 163 PSB 4610 Type Function I EEPROM Load ’1’ -> EEPROM Configuration ...
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This table lists the Pins Characteristics of the Power Management Pin No. Signal Name 90 PME_EN 98 VAUX_PR Preliminary Data Sheet Pin Count Type 164 PSB 4610 Pinning Function Reflects the state of the PME_EN ...
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This table lists the Pins Characteristics of the Power Supply Pin No. Signal Name 15 75, 88 14, 62 13, 63, 89 ________________________________________ Preliminary Data Sheet Pin Count VDD3 5 Vaux 3 VIO 2 VSS 3 165 ...
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Electrical Characteristics ________________________________________ Overview: Overview Absolute Maximum Ratings D C Characteristics ________________________________________ Pin Groups The PITA-2 has two different kind of pins: • Pins (8-12, 16-60 and 64) These pins are pow ered by VDD3 and VIO ...
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Absolute Maximum Ratings ________________________________________ This Table shows the Parameters for the Absolute Maximum Ratings Parameter Voltage pins w ith respect to ground Voltage on local pins w ith respect to ground Ambient temperature under bias Storage ...
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DC Characteristics ________________________________________ Description The DC characteristics of the PITA-2 are given in three separate tables: • pins, 5V signaling environment (VIO = 5V) • pins, 3.3V signaling environment (VIO = 3.3V) • Local pins ...
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DC Characteristics PCI Pins (5V Signaling Environment) Parameter Input High Voltage Input Low Voltage Input High Leakage Current Input Low Leakage Current Output H igh Voltage L-output voltage Input Pin Capacitance Pin Inductance PME# Input Leakage 1) exce pt ...
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DC Characteristics PCI Pins (3.3V Signaling Environment) Parameter Sym Input High V IH Voltage Input Low V IL Voltage Input I IL Leakage Current Output H igh V OH Voltage L-output V OL voltage Input Pin C Capacitance Pin ...
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DC Characteristics Local Pins Parameter Sym Input High V IH Voltage Input Low V IL Voltage Input I IL Leakage Current Output H igh V OH Voltage L-output V OL voltage ________________________________________ Preliminary Data Sheet Limit Values min max ...
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Package Outlines Preliminary Data Sheet 172 PSB 4610 Package Outlines 01.00 ...
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Configuration Space Register of the PITA-2 ________________________________________ Overview D escription of the Register Types C onfiguration Space Registers R egisters which do not occur elsew here in the Data Sheet ________________________________________ Preliminary Data Sheet Configuration Space Register of the ...
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Description of the Register Types ________________________________________ Description of the Register Types Type ________________________________________ Preliminary Data Sheet Configuration Space Register of the PITA-2 Description • read only via PC I • these bits are initialized ...
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Configuration Space Registers ________________________________________ 00h A d. Bit 00h 31:16 15:0 ________________________________________ 04h A d. Bit 04h 31 26: Preliminary Data Sheet Configuration Space Register of the PITA-2 Type Default ...
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A d. Bit 20 19:16 15:0 15: 5 ________________________________________ 08h A d. Bit 08h 31:8 7:0 Preliminary Data Sheet Configuration Space Register of the PITA-2 Type Default Register Name Value E ...
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A d. Bit 0C h 31:24 23:16 15:8 7:0 ________________________________________ 10h A d. Bit 10h 31:0 31:12 11:0 ________________________________________ 14h A d. Bit 14h 31:0 31:12 11:0 ________________________________________ Preliminary Data Sheet Configuration Space Register of the PITA-2 Type ...
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A d. Bit 18h 31:0 ________________________________________ 1Ch A d. Bit 1C h 31:0 ________________________________________ 20h A d. Bit 20h 31:0 ________________________________________ 24h A d. Bit 24h 31:0 ________________________________________ Preliminary Data Sheet Configuration Space Register of the PITA-2 Type ...
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A d. Bit 28h 31:0 31:28 27:3 2:0 ________________________________________ 2Ch A d. Bit 2C h 31:20 19:16 15:0 ________________________________________ Preliminary Data Sheet Configuration Space Register of the PITA-2 Type Default Register Name Value 0000 02C0 CardBus CIS Pointer ...
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A d. Bit 30h 31:0 ________________________________________ 34h A d. Bit 34h 31:8 7:0 ________________________________________ 38h A d. Bit 38h 31:0 ________________________________________ 3Ch A d. Bit 3C h 31:24 23:16 15:8 Preliminary Data Sheet Configuration Space Register of the ...
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A d. Bit 7:0 ________________________________________ 40h A d. Bit 40h 31:0 31:30 29: 24: 18:16 15:8 7:0 Preliminary Data Sheet Configuration Space Register of the PITA-2 Type Default Register Name Value RW ...
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A d. Bit 44h 31:24 23:16 15 14:13 12:9 8 7:2 1:0 ________________________________________ 48h A d. Bit 48h 31:0 31:30 29:28 27:20 19:18 17:10 Preliminary Data Sheet Configuration Space Register of the PITA-2 Type Default Register Name Value ...
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A d. Bit 9:8 7:0 ________________________________________ 4Ch A d. Bit 4C h 31:0 31:30 29:28 27:20 19:18 17:10 9:8 7:0 ________________________________________ Preliminary Data Sheet Configuration Space Register of the PITA-2 Type Default Register Name1 Value H/EW 00b Data_Scale ...
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A d. Bit 50h 31:0 31:20 19:18 17:10 9:8 7:0 ________________________________________ 54h A d. Bit 54h 31:0 ________________________________________ Preliminary Data Sheet Configuration Space Register of the PITA-2 Type Default Register Name Value Power Data Register 3 H 000h ...
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Registers which do not occur elsewhere in the Data Sheet ________________________________________ 00h B it 31:16 Type D efault Value D escription B it 15:0 Type D efault Value D escription ________________________________________ 04h B it 31:0 D efault Value B ...
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Type D efault Value D escription Type Value D escription Type Value D escription Type D efault Value D escription Preliminary Data Sheet Configuration Space Register ...
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B it 19:16 Type D efault Value D escription 15:10 Type D efault Value D escription Type D efault Value D escription Type D efault Value D ...
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B it 5:3 Type Value D escription Type D efault Value D escription ________________________________________ 08h B it 31:8 Type D efault Value D escription B it 7:0 Type D efault Value D escription ________________________________________ Preliminary ...
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B it 31:24 Type D efault Value D escription B it 23:16 Type D efault Value D escription B it 15:8 Type D efault Value D escription B it 7:0 Type D efault Value D escription ________________________________________ Preliminary ...
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B it 31:0 Type D efault Value D escription ________________________________________ 38h B it 31:0 Type D efault Value D escription ________________________________________ Preliminary Data Sheet Configuration Space Register of the PITA-2 Reserved H 0000 0000h Reserved Reserved H 0000 ...
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B it 31:24 Type D efault Value D escription B it 23:16 Type D efault Value D escription B it 15:8 Type D efault Value D escription B it 7:0 Type D efault Value D escription ________________________________________ Preliminary ...
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B it 31:0 Type Value D escription ________________________________________ Preliminary Data Sheet Configuration Space Register of the PITA-2 Cardbus_CIS H 00h Not supported by PITA-2 192 PSB 4610 01.00 ...
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Internal Register of the PITA ________________________________________ Overview D escription of the Register Types Internal Register R egisters w hich do not occur elsewhere in the Data Sheet ________________________________________ Preliminary Data Sheet Internal Register of the PITA 193 PSB 4610 ...
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Description of the Register Types ________________________________________ Description of the Register Types Type ________________________________________ Preliminary Data Sheet Description read only read clear • these bits are set by the internal logic • these bits can be read ...