AT90USB647 Atmel Corporation, AT90USB647 Datasheet - Page 113

• Manufacturer Part Number: AT90USB647
• Manufacturer: Atmel Corporation

Specifications of AT90USB647

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 48
• Ext Interrupts: 16
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 10
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.8.2
7593K–AVR–11/09
Timer/Counter Control Register B – TCCR0B
Note:
• Bits 3, 2 – Res: Reserved Bits
These bits are reserved bits in the AT90USB64/128 and will always read as zero.
• Bits 1:0 – WGM01:0: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see
Table 13-7.
Notes:
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is
changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a
strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the
forced compare.
Bit
Read/Write
Initial Value
Mode
0
1
2
3
4
5
6
7
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
2. BOTTOM = 0x00
1. MAX
WGM2
pare Match is ignored, but the set or clear is done at TOP. See
page 108
0
0
0
0
1
1
1
1
7
FOC0A
W
0
Waveform Generation Mode Bit Description
WGM1
= 0xFF
for more details.
0
0
1
1
0
0
1
1
6
FOC0B
W
0
WGM0
0
1
0
1
0
1
0
1
5
–
R
0
Table
Timer/Counter
Mode of
Operation
Normal
PWM, Phase
Correct
CTC
Fast PWM
Reserved
PWM, Phase
Correct
Reserved
Fast PWM
13-7. Modes of operation supported by the Timer/Counter
4
–
R
0
“Modes of Operation” on page
3
WGM02
R/W
0
OCRA
OCRA
OCRA
0xFF
0xFF
0xFF
TOP
2
CS02
R/W
0
–
–
Immediate
Immediate
Update of
OCRx at
CS01
R/W
1
0
AT90USB64/128
TOP
TOP
TOP
TOP
“Phase Correct PWM Mode” on
–
–
0
CS00
R/W
0
105).
Set on
TOV Flag
BOTTOM
BOTTOM
MAX
MAX
MAX
TOP
–
–
TCCR0B
(1)(2)
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