AT90USB647 Atmel Corporation, AT90USB647 Datasheet - Page 31

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AT90USB647

Manufacturer Part Number
AT90USB647
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT90USB647

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
48
Ext Interrupts
16
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
10
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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5.5.3
7593K–AVR–11/09
Address Latch Requirements
When the XMEM interface is enabled, the XMEM interface will override the setting in the data
direction registers that corresponds to the ports dedicated to the XMEM interface. For details
about the port override, see the alternate functions in section
interface will auto-detect whether an access is internal or external. If the access is external, the
XMEM interface will output address, data, and the control signals on the ports according to
ure 5-6
there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface
is enabled, also an internal access will cause activity on address, data and ALE ports, but the
RD and WR strobes will not toggle during internal access. When the External Memory Interface
is disabled, the normal pin and data direction settings are used. Note that when the XMEM inter-
face is disabled, the address space above the internal SRAM boundary is not mapped into the
internal SRAM.
octal latch (typically “74 x 573” or equivalent) which is transparent when G is high.
Due to the high-speed operation of the XRAM interface, the address latch must be selected with
care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at condi-
tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The
External Memory Interface is designed in compliance to the 74AHC series latch. However, most
latches can be used as long they comply with the main timing parameters. The main parameters
for the address latch are:
The External Memory Interface is designed to guaranty minimum address hold time after G is
asserted low of t
7 through Tables 30-13 on pages 407 - 409. The D-to-Q propagation delay (t
into consideration when calculating the access time requirement of the external component. The
data setup time before G low (t
wiring delay (dependent on the capacitive load).
Figure 5-5.
• D to Q propagation delay (t
• Data setup time before G low (t
• Data (address) hold time after G low (
(this figure shows the wave forms without wait-states). When ALE goes from high-to-low,
External SRAM Connected to the AVR
h
Figure 5-5
= 5 ns. Refer to t
AVR
AD7:0
A15:8
ALE
WR
RD
illustrates how to connect an external SRAM to the AVR using an
PD
SU
).
) must not exceed address valid to ALE low (t
LAXX_LD
SU
).
TH
/t
LLAXX_ST
).
D
G
Q
in “External Data Memory Timing” Tables 30-
“I/O-Ports” on page
D[7:0]
A[15:8]
A[7:0]
RD
WR
AT90USB64/128
SRAM
PD
AVLLC
) must be taken
72. The XMEM
) minus PCB
Fig-
31

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