SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 124

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Tightly-Coupled Memory Interface
5-16
The logic used to generate DRWAIT uses both the loopback scheme using DRSEQ for
inserting a wait state for a nonsequential request, and an additional signal DMAWAIT,
for stalling during DMA accesses. The FORCE_NSEQ signal is an override signal
used to force the ARM926EJ-S access to be treated as nonsequential because of an
intervening DMA access.
The A, WE and nRW inputs to the TCM are either sourced directly from the
ARM926EJ-S TCM interface, from the DMA controller, or from the capture register
(clocked by REQCLK) if the ARM926EJ-S access is postponed because of DMA
activity.
The cycle timing of the circuit shown in Figure 5-10 is shown in Figure 5-11 on
page 5-17.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Figure 5-10 DMA with single wait state for nonsequential accesses
DRADDR[17:0]
DRWD[31:0]
DRWBL[3:0]
DRRD[31:0]
DRWAIT
DRnRW
DRSEQ
DRCS
REQCLK
DMA WD
WE, nRW)
DMA (A,
FORCE_NSEQ
DMAWAIT
ARM DDI0198D
SEQ
CS
A, WE,
nRW
WD
TCM
RD