SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 70

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Memory Management Unit
3.2.1
3-6
Translation table base
31
The hardware translation process is initiated when the TLB does not contain a
translation for the requested MVA. The Translation Table Base Register (TTBR), CP15
register c2, points to the base address of a table in physical memory that contains section
or page descriptors, or both. The 14 low-order bits [13:0] of the TTBR are
Unpredictable on a read, and the table must reside on a 16KB boundary. Figure 3-1
shows the format of the TTBR.
The translation table has up to 4096 x 32-bit entries, each describing 1MB of virtual
memory. This enables up to 4GB of virtual memory to be addressed.
Figure 3-2 on page 3-7 shows the table walk process.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Translation table base
Figure 3-1 Translation Table Base Register
14 13
ARM DDI0198D
0