SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 186
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SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 186 of 248
- Download datasheet (2Mb)
Power Management
12.1
12.1.1
12-2
About power management
Dynamic power management (wait for interrupt mode)
The power management facilities provided by the ARM926EJ-S processor are:
•
•
The ARM926EJ-S processor can be put into a low-power state by the wait for interrupt
instruction:
This instruction switches the ARM926EJ-S processor into a low-power state until either
an interrupt (IRQ or FIQ) or a debug request occurs. The debug request can either be an
external debug request EDBGRQ or a debug request made by the debugger by writing
to the DBGRQ bit of the ARM9EJ-S debug control register using scan chain 2.
In wait for interrupt mode, all internal ARM926EJ-S clocks can be stopped. The switch
into the low-power state is delayed until all write buffers have been drained, and the
ARM926EJ-S memory system is in a quiescent state.
The switch into low-power state is indicated by the assertion of the STANDBYWFI
signal. If STANDBYWFI is asserted then it is guaranteed that all of ARM926EJ-S
external interfaces (AHB, TCM, and external coprocessor) are in an idle state. The
STANDBYWFI signal is intended to be used to shut down clocks to other parts of the
system, such as external coprocessors, that do not have to be clocked if the
ARM926EJ-S processor is idle.
The STANDBYWFI signal is deasserted in the second cycle following an interrupt or
a debug request. It is guaranteed that no form of access on any external interface is
started until the cycle after STANDBYWFI is deasserted. Figure 12-1 shows the
deassertion of the STANDBYWFI signal after an IRQ interrupt.
STANDBYWFI
Copyright © 2001-2003 ARM Limited. All rights reserved.
Dynamic power management (wait for interrupt mode)
Static power management (leakage control) on page 12-3.
nIRQ
CLK
Figure 12-1 Deassertion of STANDBYWFI after an IRQ interrupt
ARM DDI0198D
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