SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 143
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 143 of 248
- Download datasheet (2Mb)
6.2
6.2.1
6.2.2
ARM DDI0198D
Supported AHB transfers
Memory map
Transfer size
The ARM926EJ-S processor supports a subset of AHB transfers. The permitted AHB
transfers are described in:
•
•
•
•
•
•
The ARM926EJ-S processor is a cached processor with two AHB interfaces. It is a key
system design issue that the D side must be able to access the same memory as the I
side, with the same memory map. This is required not only to load code, but to enable
access to PC-relative literal pools, and for SWI and emulated instruction handlers to
work.
This is unlike some Harvard arrangements whereby the I-bus can be connected to the
ROM and the D-bus only connected to RAM/peripherals.
The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four
words, or bursts of eight words. Any ARM9EJ-S core requests that are not 1, 4, or 8
words in size are split into packets of these sizes. For example, an STM of 12 words is
performed on the AHB as a burst of 8 followed by a burst of 4. If a burst is interrupted
because of either a Split or Retry response, or by removal of HGRANT, then the burst
is completed as single transfers. Consequently the ARM926EJ-S processor only uses a
subset of the possible HBURST and HSIZE encodings.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Memory map
Transfer size
Mapping of level one and level two (AHB) attributes on page 6-5
Byte and halfword accesses on page 6-6
AHB system considerations on page 6-6
AHB clocking on page 6-10.
Note
Bus Interface Unit
6-3
Related parts for SAM9RL64
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
INTERVAL AND WIPE/WASH WIPER CONTROL IC WITH DELAY
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Low-Voltage Voice-Switched IC for Hands-Free Operation
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
MONOLITHIC INTEGRATED FEATUREPHONE CIRCUIT
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
AM-FM Receiver IC U4255BM-M
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Monolithic Integrated Feature Phone Circuit
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Multistandard Video-IF and Quasi Parallel Sound Processing
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
High-performance EE PLD
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
8-bit Flash Microcontroller
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
2-Wire Serial EEPROM
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
U6046BREAR WINDOW HEATING TIMER / LONG-TERM TIMER
Manufacturer:
ATMEL Corporation
Datasheet: