SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 44
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 44 of 248
- Download datasheet (2Mb)
Programmer’s Model
2-16
TCM
Instruction
TCM disabled
Instruction
TCM enabled
Instruction
TCM enabled
Instruction
TCM enabled
Data TCM
disabled
Data TCM
enabled
Data TCM
enabled
Data TCM
enabled
MMU
Disabled
Disabled
Disabled
Enabled
Disabled
Disabled
Disabled
Enabled
Effects of the Control Register on TCM interface
The M bit of the Control Register, when combined with the En bit in the respective TCM
region register c9, directly affects the TCM interface behavior, as shown in Table 2-13.
Cache
ICache
disabled
ICache
disabled
ICache
enabled
ICache
enabled
DCache
disabled
DCache
disabled
DCache
enabled
DCache
enabled
Copyright © 2001-2003 ARM Limited. All rights reserved.
Behavior
All instruction fetches are from the external memory (AHB).
All instruction fetches are from the TCM interface, or from external memory
(AHB), depending on the setting of the base address in the instruction TCM
region register. No protection checks are made. All addresses are flat mapped.
That is, VA = MVA= PA.
All instruction fetches are from the TCM interface, or from the ICache,
depending on the setting of the base address in the Instruction TCM region
register. No protection checks are made. All addresses are flat mapped. That is,
VA = MVA= PA.
All instruction fetches are from the TCM interface, or from the ICache/AHB
interface, depending on the setting of the base address in the Instruction TCM
region register. Protection checks are made. All addresses are remapped from
VA to PA, depending on the page entry. That is, the VA is translated to an MVA,
and the MVA is remapped to a PA.
All data accesses are to external memory (AHB).
All data accesses are to the TCM interface, or to the external memory, depending
on the setting of the base address in the data TCM region register. No protection
checks are made. All addresses are flat mapped. That is, VA = MVA= PA.
All data accesses are to the TCM interface or to external memory, depending on
the setting of the base address in the data TCM region register. All addresses are
flat mapped. That is, VA =MVA = PA.
All data accesses are either from the TCM interface, or from the DCache/AHB
interface, depending on the setting of the base address in the data TCM region
register. Protection checks are made. All addresses are remapped from VA to PA,
depending on the page entry. That is the VA is translated to an MVA, and the
MVA is remapped to a PA.
Table 2-13 Effects of Control Register on TCM interface
ARM DDI0198D
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