SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 164

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Coprocessor Interface
8.4
8-8
CDP
nCPMREQ is driven LOW to signal when an instruction is entering the Decode and
then the Execute stage of the pipeline. If the instruction is to be executed then the
CPPASS signal is driven HIGH during Execute. If the coprocessor can execute the
instruction immediately it drives CHSDE[1:0] with LAST. If the instruction requires a
busy-wait cycle, then the coprocessor drives CHSDE[1:0] with WAIT and then
CHSEX[1:0] with LAST. Figure 8-6 shows a CDP that is canceled due to the previous
instruction causing a Data Abort.
The CDP instruction enters the Execute stage of the pipeline and is signaled to execute
by CPPASS. In the following phase CPLATECANCEL is asserted. This causes the
coprocessor to terminate execution of the CDP instruction and for it to cause no state
changes to the coprocessor.
CPLATECANCEL can be asserted during the Memory cycle or during the Execute
cycle. The coprocessor must be able to handle instruction aborts during these two
stages.
instructions usually execute in a single cycle. Like all the previous cycles,
Copyright © 2001-2003 ARM Limited. All rights reserved.
Note
Coprocessor pipeline
CPLATECANCEL
CPINSTR[31:0]
CHSDE[1:0]
CHSEX[1:0]
nCPMREQ
CPPASS
CLK
CPRT
Fetch
Decode
LAST
Execute
Ignored
Figure 8-6 Latecanceled CDP
Memory
ARM DDI0198D
Instruction
aborted