SAM3S8B Atmel Corporation, SAM3S8B Datasheet - Page 423

• Manufacturer Part Number: SAM3S8B
• Manufacturer: Atmel Corporation

24. Peripheral DMA Controller (PDC)
24.1
24.2
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Description
Embedded Characteristics
This document describes the AHB Peripheral DMA Controller (AHB PDC) version 1.0.0.
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the
on- and/or off-chip memories. The link between the PDC and a serial peripheral is operated by
the AHB to APB bridge.
The user interface of each PDC channel is integrated into the user interface of the peripheral it
serves. The user interface of mono directional channels (receive only or transmit only), contains
two 32-bit memory pointers and two 16-bit counters, one set (pointer, counter) for current trans-
fer and one set (pointer, counter) for next transfer. The bi-directional channel user interface
contains four 32-bit memory pointers and four 16-bit counters. Each set (pointer, counter) is
used by current transmit, next transmit, current receive and next receive.
Using the PDC removes processor overhead by reducing its intervention during the transfer.
This significantly reduces the number of clock cycles required for a data transfer, which
improves microcontroller performance.
To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and
receive signals. When the programmed data is transferred, an end of transfer interrupt is gener-
ated by the peripheral itself.
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
• Handles data transfer between peripherals and memories
• Twenty-one Channels (ATSAM3S 64-pin version and 100-pin version) or Eighteen Channels
• Low bus arbitration overhead
• Next Pointer management for reducing interrupt latency requirement
(ATSAM3S 48-pin version)
– Two for each USART
– Two for the UART
– Two for each Two Wire Interface
– One for the PWM
– One for each Analog-to-digital Converter
– One for the Digital-to-Analog Converter
– Two for the MCI
– Two for the SPI
– Two for the SSC
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
SAM3S8/SD8
SAM3S8/SD8
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