SAM3S8B Atmel Corporation, SAM3S8B Datasheet - Page 681

• Manufacturer Part Number: SAM3S8B
• Manufacturer: Atmel Corporation

31.4
31.4.1
31.4.2
31.4.3
31.5
31.5.1
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
Product Dependencies
UART Operations
I/O Lines
Power Management
Interrupt Source
Baud Rate Generator
The UART pins are multiplexed with PIO lines. The programmer must first configure the corre-
sponding PIO Controller to enable I/O line operations of the UART.
Table 31-2.
The UART clock is controllable through the Power Management Controller. In this case, the pro-
grammer must first configure the PMC to enable the UART clock. Usually, the peripheral
identifier used for this purpose is 1.
The UART interrupt line is connected to one of the interrupt sources of the Nested Vectored
Interrupt Controller (NVIC). Interrupt handling requires programming of the NVIC before config-
uring the UART.
The UART operates in asynchronous mode only and supports only 8-bit character handling (with
parity). It has no clock pin.
The UART is made up of a receiver and a transmitter that operate independently, and a common
baud rate generator. Receiver timeout and transmitter time guard are not implemented. How-
ever, all the implemented features are compatible with those of a standard USART.
The baud rate generator provides the bit period clock named baud rate clock to both the receiver
and the transmitter.
The baud rate clock is the master clock divided by 16 times the value (CD) written in
UART_BRGR (Baud Rate Generator Register). If UART_BRGR is set to 0, the baud rate clock is
disabled and the UART remains inactive. The maximum allowable baud rate is Master Clock
divided by 16. The minimum allowable baud rate is Master Clock divided by (16 x 65536).
Instance
UART0
UART0
UART1
UART1
I/O Lines
Baud Rate
=
----------------------- -
16
MCK
×
URXD0
URXD1
UTXD0
UTXD1
Signal
CD
I/O Line
PA10
PA9
PB2
PB3
SAM3S8/SD8
SAM3S8/SD8
Peripheral
A
A
A
A
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