SAM3S8B Atmel Corporation, SAM3S8B Datasheet - Page 457

• Manufacturer Part Number: SAM3S8B
• Manufacturer: Atmel Corporation

25.1.14
25.1.14.1
457
457
SAM3S8/SD8
SAM3S8/SD8
Clock Switching Details
Master Clock Switching Timings
Table 25-1
from one selected clock to another one. This is in the event that the prescaler is de-activated.
When the prescaler is activated, an additional time of 64 clock cycles of the newly selected clock
has to be added.
Table 25-1.
Notes:
Table 25-2.
To
Main Clock
SLCK
PLL Clock
To
PLLA Clock
PLLB Clock
1. PLL designates either the PLLA or the PLLB Clock.
2. PLLCOUNT designates either PLLACOUNT or PLLBCOUNT.
and
From
Clock Switching Timings (Worst Case)
Clock Switching Timings between Two PLLs (Worst Case)
From
Table 25-2
PLLCOUNT x SLCK +
0.5 x Main Clock +
0.5 x Main Clock +
2.5 x PLLx Clock
Main Clock
give the worst case timings required for the Master Clock to switch
4.5 x SLCK
4 x SLCK +
PLLACOUNT x SLCK
2.5 x PLLA Clock +
3 x PLLB Clock +
1.5 x PLLB Clock
–
PLLA Clock
4 x SLCK +
4 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
2.5 x Main Clock
4 x SLCK +
5 x SLCK +
SLCK
–
PLLBCOUNT x SLCK
2.5 x PLLB Clock +
3 x PLLA Clock +
1.5 x PLLA Clock
PLLB Clock
4 x SLCK +
4 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
3 x PLL Clock +
3 x PLL Clock +
1 x Main Clock
4 x SLCK +
4 x SLCK +
PLL Clock
5 x SLCK