SAM3S8B Atmel Corporation, SAM3S8B Datasheet - Page 582

• Manufacturer Part Number: SAM3S8B
• Manufacturer: Atmel Corporation

• CKG: Transmit Clock Gating Selection
• START: Transmit Start Selection
• STTDLY: Transmit Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission
of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied.
Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emit-
ted instead of the end of TAG.
• PERIOD: Transmit Period Divider Selection
This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period
signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock.
582
582
Value
Value
0
1
2
0
1
2
3
4
5
6
7
8
SAM3S8/SD8
SAM3S8/SD8
Name
NONE
CONTINUOUS
TRANSFER
Name
CONTINUOUS
RECEIVE
RF_LOW
RF_HIGH
RF_FALLING
RF_RISING
RF_LEVEL
RF_EDGE
CMP_0
Description
None
Transmit Clock enabled only if TF Low
Transmit Clock enabled only if TF High
Description
Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and
immediately after the end of transfer of the previous data.
Receive start
Detection of a low level on TF signal
Detection of a high level on TF signal
Detection of a falling edge on TF signal
Detection of a rising edge on TF signal
Detection of any level change on TF signal
Detection of any edge on TF signal
Compare 0
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12