AD6649 Analog Devices, AD6649 Datasheet - Page 26

• Manufacturer Part Number: AD6649
• Description: IF Diversity Receiver
• Manufacturer: Analog Devices

AD6649
ADC OVERRANGE AND GAIN CONTROL
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overflow indicator provides delayed information
on the state of the analog input that is of limited value in preventing
clipping. Therefore, it is helpful to have a programmable threshold
below full scale that allows time to reduce the gain before the clip
occurs. In addition, because input signals can have significant
slew rates, latency of this function is of concern.
Using the SPI port, the user can provide a threshold above which
the FD output is active. Bit 0 of SPI Register 0x45 allows the user to
select the threshold level. As long as the signal is below the selected
threshold, the FD output remains low. In this mode, the magnitude
of the data is considered in the calculation of the condition, but
the sign of the data is not considered. The threshold detection
responds identically to positive and negative signals outside the
desired range (magnitude).
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 7 ADC clock cycles. An overrange at the
input is indicated by this bit 7 clock cycles after it occurs.
GAIN SWITCHING
The AD6649 includes circuitry that is useful in applications
either where large dynamic ranges exist or where gain ranging
amplifiers are employed. This circuitry allows digital thresholds
to be set such that an upper threshold and a lower threshold can
be programmed.
One such use is to detect when an ADC is about to reach full
scale with a particular input condition. The result is to provide
FDA OR FDB
Figure 45. Threshold Settings for FDA and FDB Signals
TIMER RESET BY
RISE ABOVE LT
Rev. A | Page 26 of 40
DWELL TIME
an indicator that can be used to quickly insert an attenuator that
prevents ADC overdrive.
Fast Threshold Detection (FDA and FDB)
The FD indicator is asserted if the input magnitude exceeds the
value programmed in the fast detect upper threshold register,
located in Register 0x47 and Register 0x48. The selected threshold
register is compared with the signal magnitude at the output of
the ADC. The fast upper threshold detection has a latency of
4 clock cycles. The upper threshold magnitude is defined by the
following equation:
The FD indicators are not cleared until the signal drops below
the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
register, located at Register 0x49 and Register 0x4A. The fast
detect lower threshold register is a 15-bit register that is
compared with the signal magnitude at the output of the ADC.
This comparison is subject to the ADC pipeline latency but is
accurate in terms of converter resolution. The lower threshold
magnitude is defined by the following equation:
The dwell time can be programmed from 1 to 65,535 sample
clock cycles by placing the desired value in the fast detect dwell
time register, located in Register 0x4B and Register 0x4C.
The operation of the upper threshold and lower threshold
registers, along with the dwell time, is shown in Figure 45.
Upper Threshold Magnitude (dBFS)
Lower Threshold Magnitude (dBFS)
= 20 log(Threshold Magnitude/2
= 20 log(Threshold Magnitude/2
UPPER THRESHOLD
DWELL TIME
LOWER THRESHOLD
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE LT
13
)
13
)
Data Sheet