AD7889 Analog Devices, AD7889 Datasheet - Page 28

• Manufacturer Part Number: AD7889
• Description: Low Voltage Controller for Touch Screens
• Manufacturer: Analog Devices

Specifications of AD7889

• Resolution (bits): 12bit
• # Chan: 6
• Sample Rate: 105kSPS
• Interface: I²C/Ser 2-Wire,Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: CSP

AD7879/AD7889
CONTROL REGISTER 2
Control Register 2 (Address 0x02) contains the ADC power
management bits, the GPIO settings, the SER/ DFR bit (to
choose the single-ended or differential method of touch screen
measurement), the averaging and median filter settings, a bit
that allows resetting of the part, and the first conversion delay
bits. Its power-on default value is 0x4040. See the Detailed
Register Descriptions section for more information about the
control registers.
For information about the averaging and median filter settings,
see the Median and Averaging Filters section. For information
about the GPIO settings, see the GPIO section.
First Conversion Delay (Control Register 2, Bits[3:0])
The first conversion delay (FCD) bits in Control Register 2
program a delay from 128 µs (default) up to 4.096 ms before
the first conversion to allow the ADC time to power up. This
delay also occurs before conversion of the X and Y coordinate
channels to allow extra time for screen settling, and after the
last conversion in a sequence to precharge PENIRQ .
Table 22. First Conversion Delay Selection
FCD[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Delay
128 µs
256 µs
384 µs
512 µs
640 µs
768 µs
896 µs
1.024 ms
1.152 ms
1.280 ms
1.536 ms
1.792 ms
2.048 ms
2.560 ms
3.584 ms
4.096 ms
15
PM1
PM0
GPIO
EN
GPIO
DAT
GPIO
DIR
GPIO
POL
Figure 31. Control Register 2
SER/
DFR
Rev. C | Page 28 of 40
AVG1 AVG0 MED1 MED0
Power Management (Control Register 2, Bits[15:14])
The power management (PM) bits in Control Register 2 allow
the power management features of the ADC to be programmed
(see Table 23). If the PM bits are set to 00, the ADC is in full
shutdown. This setting overrides any setting of the mode bits in
Control Register 1. Power management overrides the ADC modes.
Table 23. Power Management Selection
PM1
0
0
1
1
0
1
0
1
PM0
RST
SW/
FCD3 FCD2 FCD1 FCD0
Function
Full shutdown; ADC, oscillator, bias, and temp-
erature sensor are turned off. The only way to
exit this mode is to write to the part over the
serial interface and change the PM bits. This
setting overrides any other setting on the
part, including the ADC mode bits.
The analog blocks to be powered down
depend on the ADC mode setting. In master
mode, the ADC, bias, temperature sensor, and
oscillator are powered down and must wake
up when the user touches the screen. In slave
mode, the ADC and temperature sensor are
powered down when not being used. They
wake up automatically when required. The
oscillator and bias are powered up because
they are needed to measure time. This setting
also applies to the single-conversion mode.
The ADC, bias, and oscillator are powered up
continuously, irrespective of ADC mode.
Same as 01.
0