AD7889 Analog Devices, AD7889 Datasheet - Page 34

• Manufacturer Part Number: AD7889
• Description: Low Voltage Controller for Touch Screens
• Manufacturer: Analog Devices

Specifications of AD7889

• Resolution (bits): 12bit
• # Chan: 6
• Sample Rate: 105kSPS
• Interface: I²C/Ser 2-Wire,Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: CSP

AD7879/AD7889
I
The AD7879-1/AD7889-1 support the industry standard 2-wire
I
I
allows both register write and register readback operations. The
AD7879-1/AD7889-1 are always slave devices on the I
interface bus.
The devices have a 7-bit device address, Address 0101 1XX. The
lower two bits are set by tying the ADD0 and ADD1 pins high or
low. The AD7879-1/AD7889-1 respond when the master device
sends its device address over the bus. The AD7879-1/AD7889-1
cannot initiate data transfers on the bus.
Table 25. I
ADD1
0
0
1
1
Data Transfer
Data is transferred over the I
The master initiates a data transfer by establishing a start
condition, defined as a high-to-low transition on the serial data
line, SDA, while the serial clock line, SCL, remains high. This
indicates that an address/data stream follows.
2
2
2
C serial interface protocol. The two wires associated with the
C timing are the SCL and SDA inputs. SDA is an I/O pin that
C-COMPATIBLE INTERFACE
DOUT
SCL
DIN
CS
2
C Device Addresses for the AD7879-1/AD7889-1
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS CAN BE READ BACK CONTINUOUSLY.
2. THE 16-BIT COMMAND WORD MUST BE WRITTEN ON DIN: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE DOUT PIN.
4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
5. X DENOTES DON’T CARE.
6. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READBACK OPERATION:
XXX XXX XXX
CW
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 1 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS)
15
ADD0
0
1
0
1
1
ENABLE WORD
CW
14
2
CW
13
3
XXX XXX XXX XXX XXX XXX XXX
CW
12
2
C serial interface in 8-bit bytes.
4
CW
11
5
R/W
I
0101 100
0101 101
0101 110
0101 111
CW
10
2
C Address
16-BIT COMMAND WORD
6
CW
9
7
CW
8
8
STARTING REGISTER ADDRESS
CW
7
Figure 42. Sequential Register Readback, SPI Timing
9
CW
6
10
2
CW
XXX XXX XXX
C serial
5
11
CW
4
12
Rev. C | Page 34 of 40
CW
3
13
XXX XXX
CW
2
14
CW
1
15
All slave peripherals connected to the serial bus respond to the
start condition and shift in the next eight bits, consisting of a
7-bit address (MSB first) plus a R/ W bit that determines the
direction of the data transfer. The peripheral whose address
corresponds to the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as the
acknowledge bit. All other devices on the bus then remain idle
while the selected device waits for data to be read from or written
to it. If the R/ W bit is a 0, the master writes to the slave device.
If the R/ W bit is a 1, the master reads from the slave device.
Data is sent over the serial bus in a sequence of nine clock
pulses (eight bits of data followed by an acknowledge bit from
the slave device). Transitions on the data line must occur during
the low period of the clock signal and remain stable during the
high period because a low-to-high transition when the clock
is high can be interpreted as a stop signal. The number of data
bytes transmitted over the serial bus in a single read or write
operation is limited only by what the master and slave devices
can handle.
When all data bytes are read or written, a stop condition is
established. A stop condition is defined by a low-to-high
transition on SDA while SCL remains high. If the AD7879-1/
AD7889-1 encounter a stop condition, they return to the idle
condition.
XXX
CW
0
16
D15
X
17
READBACK DATA FOR
STARTING REGISTER
D14
X
18
ADDRESS
D1
X
31
D0
X
32
D15
NEXT REGISTER ADDRESS
X
33
READBACK DATA FOR
D14
X
34
D1
X
47
D0
X
48
D15
X
49