AD9268 Analog Devices, AD9268 Datasheet - Page 10

• Manufacturer Part Number: AD9268
• Description: 16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9268

• Resolution (bits): 16bit
• # Chan: 2
• Sample Rate: 125MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9268
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
Timing Diagrams
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
CH A/CH B DATA
CH A/CH B DATA
DCOA/DCOB
DCOA/DCOB
CLK+
CLK–
CLK+
CLK–
VIN
VIN
Conditions
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge
Time required for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge
N – 1
N – 1
Figure 3. CMOS Interleaved Output Mode Data Output Timing
t
t
Figure 2. CMOS Default Output Mode Data Output Timing
CH
CH
t
DCO
N – 13
t
t
PD
PD
N
N
N – 12
t
t
CH A
t
A
t
A
CLK
Rev. A | Page 10 of 44
CLK
t
DCO
t
t
N – 12
SKEW
SKEW
N – 12
CH B
N + 1
N + 1
N – 11
CH A
N – 11
N – 11
CH B
N + 2
N + 2
N – 10
CH A
N – 10
N – 10
N + 3
N + 3
CH B
CH A
N – 9
N – 9
N + 4
CH B
N – 9
N + 4
CH A
N – 8
N – 8
N + 5
N + 5
Limit
0.3 ns typ
0.40 ns typ
2 ns min
2 ns min
40 ns min
2 ns min
2 ns min
10 ns min
10 ns min
10 ns min
10 ns min