AD9600 Analog Devices, AD9600 Datasheet - Page 29

• Manufacturer Part Number: AD9600
• Description: 10-Bit, 105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9600

• Resolution (bits): 10bit
• # Chan: 2
• Sample Rate: 150MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Table 12. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin
AGND
AVDD
Digital Output Enable Function (OEB)
The AD9600 has a flexible three-state ability for the digital
output pins. The three-state mode can be enabled by using the
SMI SDO/OEB pin or the SPI interface. If the SMI SDO/OEB pin
is low, the output data drivers are enabled. If the SMI SDO/OEB pin
is high, the output data drivers are placed into a high impedance
state. This output enable function is not intended for rapid access
to the data bus. Note that OEB is referenced to the digital output
driver supply (DRVDD) and should not exceed that supply voltage.
When the device uses the SPI interface, each channel’s data and
fast detect output pins can be independently three-stated by
using the output enable bar bit in Register 0x14.
Table 13. Output Data Format
Input (V)
(VIN+ ) − (VIN− )
(VIN+ ) − (VIN− )
(VIN+ ) − (VIN− )
(VIN+ ) − (VIN− )
(VIN+ ) − (VIN− )
SCLK/DFS
Offset binary (default)
Twos complement
Condition (V)
< −VREF − 0.5 LSB
= –VREF
= 0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
SDIO/DCS
DCS disabled
DCS enabled (default)
Binary Output Mode
00 0000 0000
00 0000 0000
10 0000 0000
11 1111 1111
11 1111 1111
Rev. B | Page 29 of 72
TIMING
The AD9600 provides latched data with a pipeline delay of
12 clock cycles. Data outputs are available one propagation
delay (t
The length of the output data lines and the loads placed on them
should be minimized to reduce transients within the AD9600.
These transients can degrade the dynamic performance of the
converter. The lowest typical conversion rate of the AD9600 is
typically 10 MSPS. At clock rates below 10 MSPS, dynamic
performance may degrade.
Data Clock Output (DCO)
The AD9600 provides two data clock output (DCO) signals
intended for capturing the data in an external register. The data
outputs are valid on the rising edge of DCO, unless the polarity
has been changed via the SPI. See the timing diagrams shown
in Figure 2 and Figure 3 for more information.
PD
) after the rising edge of the clock signal.
10 0000 0000
Twos Complement Mode
10 0000 0000
00 0000 0000
01 1111 1111
01 1111 1111
AD9600
Overrange
1
0
0
0
1