AD9600 Analog Devices, AD9600 Datasheet - Page 31

• Manufacturer Part Number: AD9600
• Description: 10-Bit, 105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9600

• Resolution (bits): 10bit
• # Chan: 2
• Sample Rate: 150MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

When the fast detect mode select bits are set to 0b001, 0b010, or
0b011, a subset of the fast detect output pins is available. In these
modes, the fast detect output pins have a latency of six clock cycles.
Table 16 shows the corresponding ADC input levels when the
fast detect mode select bits are set to 0b001 (that is, when ADC
fast magnitude is presented on the FD [3:1] pins).
Table 16. ADC Fast Magnitude Nominal Levels with
Fast Detect Mode Select Bits = 001
ADC Fast Magnitude on
FD [3:1] Pins
000
001
010
011
100
101
110
111
When the fast detect mode select bits are set to 0b010 or 0b011
(that is, when ADC fast magnitude is presented on the FD [3:2]
pins), the LSB is not provided. The input ranges for this mode
are shown in Table 17.
Table 17. ADC Fast Magnitude Nominal Levels with
Fast Detect Mode Select Bits = 010 or 011
ADC Fast Magnitude on
FD [3:2] Pins
00
01
10
11
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and therefore is
subject to the 12-clock-cycle latency. An overrange at the input
would be indicated by this bit 12 clock cycles after it occurred.
GAIN SWITCHING
The AD9600 includes circuitry that is useful in applications
either where large dynamic ranges exist or where gain ranging
converters are employed. This circuitry allows digital thresholds
to be set such that an upper threshold and a lower threshold can
be programmed. Fast detect mode select bit = 010 through fast
detect mode select bit = 101 support various combinations of the
gain switching options.
One such use is to detect when an ADC is about to reach full
scale with a particular input condition. The result is to provide
an indicator that can be used to quickly insert an attenuator that
prevents ADC overdrive.
Nominal Input
Magnitude
Below FS (dB)
<−14.5
−14.5 to −7
−7 to −3.25
−3.25 to 0
Nominal Input
Magnitude
Below FS (dB)
<−24
−24 to −14.5
−14.5 to −10
−10 to −7
−7 to −5
−5 to −3.25
−3.25 to −1.8
−1.8 to 0
−30.14 to −12.04
−18.07 to −8.52
−12.04 to −6.02
−4.08 to −1.16
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to −12.04
−18.07 to −6.02
−8.52 to −2.5
−4.08 to 0
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to −18.07
−8.52 to −4.08
−6.02 to −2.5
−2.5 to 0
Rev. B | Page 31 of 72
Coarse Upper Threshold (C_UT)
The coarse upper threshold indicator is asserted if the ADC fast
magnitude input level is greater than the level programmed in the
coarse upper threshold register at Address 0x105 [2:0]. The coarse
upper threshold output is output two clock cycles after the level
is exceeded at the input and therefore provides a fast indication
of the input signal level. The coarse upper threshold levels are
shown in Table 18. This indicator remains asserted for a mini-
mum of two ADC clock cycles or until the signal drops below
the threshold level.
Table 18. Coarse Upper Threshold Levels
Coarse Upper Threshold
(Register 0x105 [2:0])
000
001
010
011
100
101
110
111
Fine Upper Threshold (F_UT)
The fine upper threshold indicator is asserted if the input magni-
tude exceeds the value programmed in the fine upper threshold
register located at Address 0x106 and Address 0x107. The 13-bit
threshold register is compared with the signal magnitude at the
output of the ADC. This comparison is subject to the ADC clock
latency but is accurate in terms of the converter resolution. The
fine threshold magnitude is defined by the following equation:
Fine Lower Threshold (F_LT)
The fine lower threshold indicator is asserted if the input magni-
tude is less than the value programmed in the fine lower threshold
register located at Address 0x108 and Address 0x109. The fine
lower threshold register is a 13-bit register that is compared with
the signal magnitude at the output of the ADC. This comparison
is subject to the ADC clock latency but provides a comparison
accurate to the converter resolution. The fine threshold magnitude
is defined in Equation 1.
The operation of the F_UT and F_LT indicators is shown in
Figure 66.
dBFS = 20 log(Threshold Magnitude/2
C_UT Is Active When Signal
Magnitude Below FS
Is Greater Than (dB)
<−24
−24
−14.5
−10
−7
−5
−3.25
−1.8
13
)
AD9600
(1)