AD9600 Analog Devices, AD9600 Datasheet - Page 47

• Manufacturer Part Number: AD9600
• Description: 10-Bit, 105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9600

• Resolution (bits): 10bit
• # Chan: 2
• Sample Rate: 150MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

APPLICATIONS INFORMATION
DESIGN GUIDELINES
When designing the AD9600 into a system, the designer
should, before starting design and layout, become familiar with
these guidelines, which discuss the special circuit connections
and layout requirements for certain pins.
Power and Ground Recommendations
When connecting power to the AD9600, the designer should use
two separate 1.8 V supplies: one supply should be used for AVDD
and DVDD and a separate supply for DRVDD. The AVDD and
DVDD supplies, although derived from the same source, should be
isolated with a ferrite bead or filter choke and have separate
decoupling capacitors. The user can employ several different
decoupling capacitors to cover both high and low frequencies.
These should be located close to the point of entry at the PC
board level and close to the part’s pins with minimal trace
length.
A single PC board ground plane should be sufficient when
using the AD9600. With proper decoupling and smart parti-
tioning of the PC board’s analog, digital, and clock sections,
optimum performance can be easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
To achieve the best electrical and thermal performance of the
AD9600, the exposed paddle on the underside of the ADC must
be connected to analog ground (AGND). A continuously exposed
(no solder mask) copper plane on the PCB should mate to the
exposed paddle, Pin 0, of the AD9600. In addition, the copper
plane should have several vias to achieve the lowest possible
resistive thermal path for heat dissipation to flow through the
bottom of the PCB, and these vias should be filled or plugged
with nonconductive epoxy.
Rev. B | Page 47 of 72
To maximize the coverage and adhesion between the ADC and
PCB, overlay a silkscreen to partition the continuous plane on
the PCB into several uniform sections. This provides several tie
points between the ADC and PCB during the reflow process.
Using one continuous plane with no partitions guarantees only
one tie point between the ADC and PCB. See the evaluation board
layout figures (Figure 84 to Figure 91) for an example of a PCB
layout. For detailed information on packaging and the PCB layout
of chip scale packages, see the AN-772 Application Note, A Design
and Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP).
CML
The CML pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 47.
RBIAS
The AD9600 requires the user to place a 10 kΩ resistor between
the RBIAS pin and ground. This register sets the master current
reference of the ADC core and should have at least a 1% tolerance.
Reference Decoupling
The VREF pin should be externally decoupled to ground with a
low-ESR 1.0 μF capacitor in parallel with a 0.1 μF ceramic low-
ESR capacitor.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade the converter’s
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9600 in order to keep these signals from transitioning at the
converter inputs during critical sampling periods.
AD9600