AD7277 Analog Devices, AD7277 Datasheet - Page 17

• Manufacturer Part Number: AD7277
• Description: 3 MSPS,10-Bit ADC in 6-Lead TSOT
• Manufacturer: Analog Devices

Specifications of AD7277

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 3MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOP,SOT

The load regulation of the REF193 is typically 10 ppm/mA
(REF193, V
for the 5 mA drawn from it. When V
corresponds to an error of 0.204 LSB, 0.051 LSB, and 0.0128 LSB
for the AD7276, AD7277, and AD7278, respectively. For applica-
tions where power consumption is of concern, use the power-down
mode of the ADC and the sleep mode of the REF19x reference to
improve power performance. See the Modes of Operation section.
Table 8 provides typical performance data with various
references used as a V
Table 8. AD7276 Performance (Various Voltage References IC)
Reference Tied to V
AD780 @ 3 V
AD780 @ 2.5 V
REF193
Analog Input
Figure 23 shows an equivalent circuit of the analog input structure
of the AD7276/AD7277/AD7278. The two diodes, D1 and D2,
provide ESD protection for the analog inputs. Care must be taken
to ensure that the analog input signal never exceeds the supply
rails by more than 300 mV. Signals exceeding this value cause
these diodes to become forward biased and to start conducting
current into the substrate. These diodes can conduct a maximum
current of 10 mA without causing irreversible damage to the
part. Capacitor C1 in Figure 23 is typically about 4 pF and can
primarily be attributed to pin capacitance. Resistor R1 is a
lumped component made up of the on resistance of a switch.
This resistor is typically about 75 Ω. Capacitor C2 is the ADC
sampling capacitor and has a capacitance of 4 pF typically when
in hold mode and 32 pF typically when in track mode. For ac
applications, removing high frequency components from the
analog input signal is recommended by using a band-pass filter
on the relevant analog input pin. In applications where the
harmonic distortion and signal-to-noise ratio are critical, the
analog input should be driven from a low impedance source.
0V TO V
Figure 22. REF193 as Power Supply to the AD7276/AD7277/AD7278
680nF
INPUT
DD
S
= 5 V), which results in an error of 50 ppm (150 μV)
V
V
GND
DD
IN
0.1µF
AD7276/
AD7277/
AD7278
DD
DD
source with the same setup conditions.
TANT
1µF
3V
SNR Performance, 1 MHz Input
71.3 dB
70.1 dB
70.9 dB
SDATA
SCLK
INTERFACE
CS
SERIAL
REF193
DD
= 3 V from the REF193, it
10µF
0.1µF
µC/µP
DSP/
5V
SUPPLY
Rev. C | Page 17 of 28
Large source impedances significantly affect the ac performance
of these ADCs and can necessitate the use of an input buffer
amplifier. The AD8021 op amp is compatible with these devices;
however, the choice of the op amp is a function of the particular
application.
When no amplifier is used to drive the analog input, the source
impedance should be limited to a low value. The maximum source
impedance depends on the amount of THD that can be tolerated.
The THD increases as the source impedance increases and per-
formance degrades. Figure 16 shows a graph of the THD vs. the
analog input frequency for different source impedances when
using a supply voltage of 3 V and sampling at a rate of 3 MSPS.
Digital Inputs
The digital inputs applied to the AD7276/AD7277/AD7278 are
not limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs applied to the AD7276/AD7277/
AD7278 can be 6 V and are not restricted by the V
limit of the analog inputs. For example, if the AD7276/AD7277/
AD7278 are operated with a V
be used on the digital inputs. However, it is important to note
that the data output on SDATA still has 3 V logic levels when
V
by the V
avoided. For example, unlike with the analog inputs, with the
digital inputs, if
risk of latch-up.
DD
= 3 V. Another advantage of SCLK and
V
DD
IN
+ 0.3 V limit is that power supply sequencing issues are
4pF
C1
Figure 23. Equivalent Analog Input Circuit
CS
or SCLK is applied before V
V
DD
D1
D2
AD7276/AD7277/AD7278
CONVERSION PHASE—SWITCH OPEN
TRACK PHASE—SWITCH CLOSED
DD
of 3 V, then 5 V logic levels can
R1
CS
C2
not being restricted
DD
, there is no
DD
+ 0.3 V